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1. 发明专利

JP2005260228A Integrated circuit device including vertical dram and manufacturing method therefor 审中-公开
标题翻译：集成电路设备，包括垂直DRAM及其制造方法
公开(公告)号：JP2005260228A
公开(公告)日：2005-09-22
申请号：JP2005059899
申请日：2005-03-04
申请人： Internatl Business Mach Corp , インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation
发明人： RAMACHANDORA DEIVAKARUNI , GLUSCHENKOV OLEG , KWON OH-JUNG , RAJEEV MALIK
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/44 , H01L21/8234 , H01L21/8242 , H01L23/52 , H01L27/088 , H01L27/108 , H01L29/423 , H01L29/49
CPC分类号： H01L27/10894 , H01L27/10861 , H01L27/10891 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a structure to resolve problems in word line continuity and support region punch-through, and to provide a manufacturing method therefor. SOLUTION: An integrated circuit comprises at least one semiconductor memory array and a logic circuit. The memory array includes conductive word lines. The logic circuit includes a logic transistor having a conductive gate. The gate of the logic transistor and the word lines are composed of polysilicon and metal layers. In the word lines, the metal layer is thicker than the polysilicon layer. In the gate of the logic transistor, the metal layer is thinner than the polysilicon layer. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供解决字线连续性和支撑区域穿透中的问题的结构，并提供其制造方法。解决方案：集成电路包括至少一个半导体存储器阵列和逻辑电路。存储器阵列包括导电字线。逻辑电路包括具有导电栅极的逻辑晶体管。逻辑晶体管的栅极和字线由多晶硅和金属层组成。在字线中，金属层比多晶硅层厚。在逻辑晶体管的栅极中，金属层比多晶硅层薄。版权所有（C）2005，JPO＆NCIPI

2. 发明专利

JP2004128489A Memory cell structure and its manufacturing method 有权
公开(公告)号：JP2004128489A
公开(公告)日：2004-04-22
申请号：JP2003310714
申请日：2003-09-02
申请人： Internatl Business Mach Corp , インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation
发明人： RADENS CARL J , RAMACHANDORA DEIVAKARUNI , MANDELMAN JACK A
IPC分类号： H01L21/334 , H01L21/8242 , H01L27/108 , H01L29/94
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10867 , H01L29/66181 , H01L29/945
摘要： PROBLEM TO BE SOLVED: To make the interaction between straps smaller than that of the conventional ones. SOLUTION: Each deep trench has its rim in a direction orthogonal to its depth direction. A buried strap 60 extends along the rim. The length of the buried strap 60 is limited to 5-20% of the full length of the rim, and is smaller than one lithography feature size. The buried strap 60, which lies along the rim, is preferably curved and positioned along only one corner of the rim. This structure is useful especially for sub-8F 2 cells. COPYRIGHT: (C)2004,JPO

3. 发明专利

JP2004088098A Formation of self-aligned buried strap connector 有权
公开(公告)号：JP2004088098A
公开(公告)日：2004-03-18
申请号：JP2003287154
申请日：2003-08-05
申请人： Internatl Business Mach Corp , インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation
发明人： CHUDZIK MICHAEL P , BEINTNER JOCHEN , RAMACHANDORA DEIVAKARUNI , JAMMY RAJARAO
IPC分类号： H01L21/334 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10867 , H01L27/10841 , H01L29/66181
摘要： PROBLEM TO BE SOLVED: To provide a method to form a three-dimensional electrical structure which brings two circuit elements separated in the horizontal and vertical directions into contact, regarding the formation of structures including a DRAM cell comprising a vertical transistor.
SOLUTION: A temporary insulator layer is deposited, and a vertical spacer is formed on the trench walls above the temporary insulator, then the insulator is removed to expose the substrate walls. Next, dopant is diffused into the substrate walls to form a self-aligned extension of a buried strap, and a final gate insulator is deposited, then the upper portion of a DRAM cell is formed.
COPYRIGHT: (C)2004,JPO

4. 发明专利

JP2006041516A Patterned strained semiconductor substrate and device 有权
标题翻译：图形应变半导体衬底和器件
公开(公告)号：JP2006041516A
公开(公告)日：2006-02-09
申请号：JP2005208400
申请日：2005-07-19
申请人： Internatl Business Mach Corp , インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation
发明人： CHENG KANGGUO , RAMACHANDORA DEIVAKARUNI
IPC分类号： H01L21/8234 , H01L27/088 , H01L29/786
CPC分类号： H01L29/1054 , H01L21/823412 , H01L29/739 , H01L29/78687
摘要： PROBLEM TO BE SOLVED: To provide a method and a structure for forming strained and non-strained areas on one substrate. SOLUTION: A disclosed method comprises: a process of forming a pattern of strained and relaxed materials on a substrate 101; a process of forming a strained device 129 in the strained material; and a process of forming a non-strained device 131 in the relaxed material. The strained material is silicon (Si) in a tensile or compressive state, and the relaxed material is Si in a normal state. A buffer layer 113 which is made of silicon germanium (SiGe), silicon carbon (SiC), or a similar material and has a different lattice constant/structure from that of the substrate, and a relaxed layer 111 are formed on the substrate 101. The strained material is placed in the tensile or compressive state. In another embodiment, carbon-doped silicon or germanium-doped silicon is used to form the strained material. The structure includes a multilayer substrate having strained and non-strained materials on which a pattern is formed. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供在一个基板上形成应变和非应变区域的方法和结构。解决方案：所公开的方法包括：在衬底101上形成应变和松弛材料的图案的工艺; 在应变材料中形成应变器件129的工艺; 以及在松弛材料中形成非应变器件131的工艺。应变材料是处于拉伸或压缩状态的硅（Si），松弛材料是Si处于正常状态。在衬底101上形成由硅锗（SiGe），硅碳（SiC）或类似材料制成并且具有与衬底的晶格常数/结构不同的晶格常数/结构的缓冲层113。应变材料处于拉伸或压缩状态。在另一个实施例中，使用碳掺杂硅或锗掺杂硅来形成应变材料。该结构包括具有应变和非应变材料的多层基底，其上形成图案。版权所有（C）2006，JPO＆NCIPI

5. 发明专利

JP2004040095A Dram cell and method for forming the same 有权
公开(公告)号：JP2004040095A
公开(公告)日：2004-02-05
申请号：JP2003178790
申请日：2003-06-23
申请人： Internatl Business Mach Corp , インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation
发明人： MANDELMAN JACK A , RAMACHANDORA DEIVAKARUNI , YANG HAINING
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10876 , H01L27/10864 , H01L27/10888 , H01L27/10891
摘要： PROBLEM TO BE SOLVED: To provide a DRAM array employing a small vertical transistor of bitline capacitance. SOLUTION: A DRAM array comprising DRAM cells employing the vertical transistor increases electrical reliability and reduces the bitline capacitance by the use of an asymmetric structure in connection between a wordline 310 and the transistor. Thereby, the DRAM array permits the use of wider connection between the wordline 310 and a transistor electrode. Also, the word line 310 is used as an etch stop to protect a transistor gate 205 during the patterning of the wordline 310. COPYRIGHT: (C)2004,JPO

6. 发明专利

JP2005051246A Vertical dram device having self-aligning function of shaping upper trench, and method for forming the same 有权
标题翻译：具有形成上光束的自对准功能的垂直DRAM器件及其形成方法
公开(公告)号：JP2005051246A
公开(公告)日：2005-02-24
申请号：JP2004222267
申请日：2004-07-29
申请人： Internatl Business Mach Corp , インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation
发明人： CHENG KANGGUO , RAMACHANDORA DEIVAKARUNI , SUNG C Y
IPC分类号： H01L27/108 , H01L21/336 , H01L21/8242 , H01L27/02
CPC分类号： H01L27/10876 , H01L27/0207 , H01L27/10864 , H01L27/1087 , H01L29/945
摘要： PROBLEM TO BE SOLVED: To provide a method and a structure for a vertical DRAM device having a self-aligning function of shaping upper trench. SOLUTION: The method and the structure of a memory storage cell in a semiconductor substrate include forming of a dopant source material, covering a lower portion of a deep trench formed in the substrate. The upper portion of the trench is generally shaped into a rectangular form, and an embedded electrode plate of a trench capacitor by annealing the dopant source material. The embedded electrode plate is self-aligned, with respect to the shaped upper-portion of the trench. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：解决的问题：提供一种具有成形上沟槽自对准功能的垂直DRAM器件的方法和结构。解决方案：半导体衬底中的存储器存储单元的方法和结构包括形成掺杂剂源材料，覆盖形成在衬底中的深沟槽的下部。沟槽的上部通常通过对掺杂剂源材料进行退火而成形为矩形形状，以及沟槽电容器的嵌入式电极板。嵌入式电极板相对于沟槽的成形上部自对准。版权所有（C）2005，JPO＆NCIPI

7. 发明专利

JP2005019994A Method for forming buried plate in trench capacitor 有权
标题翻译：在TRENCH电容器中形成BURIED板的方法
公开(公告)号：JP2005019994A
公开(公告)日：2005-01-20
申请号：JP2004183609
申请日：2004-06-22
申请人： Internatl Business Mach Corp , インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation
发明人： CHENG KANGGUO , RAMACHANDORA DEIVAKARUNI
IPC分类号： H01L27/108 , H01L21/02 , H01L21/3215 , H01L21/8242
CPC分类号： H01L28/60 , H01L21/3215 , H01L27/1087
摘要： PROBLEM TO BE SOLVED: To provide a method for forming a buried plate in a trench capacitor, thereby overcoming limitation in the conventional method.
SOLUTION: A dopant source material such as ASG is completely filled into a trench. Next, a recess is formed on this dopant source material, and a collar material is deposited thereon. Thus, a collar is formed on the upper side portion of the trench. After the buried plate is formed through drive-in of the dopant, the dopant source material is removed and the collar material may be removed.
COPYRIGHT: (C)2005,JPO&NCIPI

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