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1. 发明专利

JP2003051200A Test circuit for semiconductor memory device 有权
标题翻译：半导体存储器件的测试电路
公开(公告)号：JP2003051200A
公开(公告)日：2003-02-21
申请号：JP2002144783
申请日：2002-05-20
申请人： Hitachi Ltd , Texas Instr Japan Ltd , 日本テキサス・インスツルメンツ株式会社 , 株式会社日立製作所
发明人： SUKEGAWA SHUNICHI , SHIOZAKI SHUZO , MATSUURA NOBUMI , MURANAKA MASAYA
IPC分类号： G01R31/28 , G11C11/401 , G11C29/00 , G11C29/14 , H01L21/822 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To suppress increase of area of a test circuit in a semiconductor chip and to increase kinds of tests.
SOLUTION: This test mode register circuit is constituted of a decoder circuit 60 decoding an address indicating a test mode, and a latch circuit 61 latching an output of the decoder circuit 60 being a decode-result. This latch circuit 61 is reset by only a test enable-signal TEN outputted from a test enable-signal generating circuit. In this test mode register circuit, test functions to which conventional test modes are divided into each element are allotted to the decoder circuit 60 as a set address value, and each test mode is realized by multi- selecting a plurality of test mode register circuits.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：抑制半导体芯片中的测试电路的面积的增加和增加测试的种类。解决方案：该测试模式寄存器电路由译码器电路60构成，解码器电路60解码表示测试模式的地址，锁存电路61锁存解码器电路60的输出作为解码结果。该锁存电路61仅由从测试使能信号发生电路输出的测试使能信号TEN复位。在该测试模式寄存器电路中，将常规测试模式划分为每个元件的测试功能分配给解码器电路60作为设置地址值，并且通过多选择多个测试模式寄存器电路实现每个测试模式。

2. 发明专利

JPH11273349A Semiconductor storage device 失效
标题翻译：半导体存储设备
公开(公告)号：JPH11273349A
公开(公告)日：1999-10-08
申请号：JP7685498
申请日：1998-03-25
申请人： Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： MURANAKA MASAYA
IPC分类号： G11C11/409
摘要： PROBLEM TO BE SOLVED: To obtain a semiconductor memory device which eliminates a need of precharging electric power after a write operation in an input/output-line precharging system, which reduces the driving electric power of an input/output line in the write operation because the driving electric power of the input/output line in the write operation can be supplied from an external power supply and whose high speed and low noise are realized.
SOLUTION: A semiconductor memory device is a 64M.DRAM according to the specifications of a direct RAM bus. It is constituted of a DRAM core, composed of a memory array or the like, and of an interface logic circuit. In a standby operation by a sensing operation, an input/output line IO is precharged to an HVC level by a precharging circuit. In a write operation, write data is output to the input/output line IO. The driving voltage of the input/output line IO in the write operation is an external power-supply voltage VDD. After the write operation is finished, a column selection signal line YS becomes a low level, an equalization circuit is turned on, and the input/output line IO is equalized to a 1/2 VDD level.
COPYRIGHT: (C)1999,JPO
摘要翻译：要解决的问题：为了获得在输入/输出线预充电系统中在写入操作之后不需要预充电电力的半导体存储器件，这降低了写操作中输入/输出线的驱动电力，因为可以从外部电源提供写入操作中的输入/输出线的驱动电力，并实现其高速和低噪声。解决方案：根据直接RAM总线的规格，半导体存储器件是64M.DRAM。它由由存储器阵列等构成的DRAM内核和接口逻辑电路构成。在通过感测操作的待机操作中，输入/输出线IO由预充电电路预充电到HVC电平。在写入操作中，写数据被输出到输入/输出线IO。在写入操作中输入/输出线IO的驱动电压是外部电源电压VDD。在写操作完成之后，列选择信号线YS成为低电平，均衡电路导通，输入/输出线IO等于1/2 VDD电平。

3. 发明专利

JP2000076895A Semiconductor integrated circuit device 审中-公开
标题翻译：半导体集成电路设备
公开(公告)号：JP2000076895A
公开(公告)日：2000-03-14
申请号：JP24023298
申请日：1998-08-26
申请人： Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： ITO YUTAKA , MURANAKA MASAYA , OYAMADA MASAHIRO , TAKAHASHI AKIRA , SAKASHITA TADAMICHI , MATSUMOTO YOSHINORI
IPC分类号： G01R31/28 , G11C11/401 , G11C11/407 , G11C29/00 , G11C29/06
摘要： PROBLEM TO BE SOLVED: To shorten the applied time of stress voltage, and to conduct a screening test efficiently in a short time.
SOLUTION: When a bender test mode conducting a voltage acceleration test is entered, a test signal TM1 at a low level is input to step-down power circuits 15, 16 from a bender test circuit, a transistor 19 is turned on, and operation as an operational amplifier is stopped. An inverter 27 reaches a high-level output and a transistor 26 is turned on, a transistor 22 is turned on and voltage in the same extent as power-supply voltage Vcc is output from the step-down power circuits 15, 16, and optimum voltage stress is applied even to a peripheral circuit driven by power-supply voltage Vcc and step-down voltage VPERI, VDL and the voltage acceleration test can be performed.
COPYRIGHT: (C)2000,JPO
摘要翻译：要解决的问题：缩短应力电压的施加时间，并在短时间内有效进行筛选试验。解决方案：进入进行电压加速试验的弯曲试验模式时，从弯曲试验电路向低压电路15,16输入低电平的试验信号TM1，将晶体管19导通，将其作为运算放大器停止。反相器27到达高电平输出并且晶体管26导通，晶体管22导通，并且从降压功率电路15,16输出与电源电压Vcc相同程度的电压，并且最佳甚至对由电源电压Vcc和降压电压VPERI，VDL驱动的外围电路施加电压应力，并且可以执行电压加速度测试。

4. 发明专利

JPH11273348A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：JPH11273348A
公开(公告)日：1999-10-08
申请号：JP7574298
申请日：1998-03-24
申请人： Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： MURANAKA MASAYA
IPC分类号： G11C11/409 , G11C11/407
摘要： PROBLEM TO BE SOLVED: To control supply of a high voltage from an internal voltage generating circuit in order to reduce power consumption of a device by forming a drive circuit with a self-boost voltage booster circuit and a level holding circuit and then supplying the power from a low voltage external power supply at the time of driving an output node with a large amplitude.
SOLUTION: A self-boost voltage booster circuit operates with a low voltage external power supply voltage VDD, for example, 3.3 V and charges a capacitor C1 when the input signal IN changes to the low level from high level. Thereafter, when NMOS transistor TN 15 turns off and then the node e changes to the high level, charges of the capacitor C1 are transferred to the level holding circuit and the level of output signal out is boosted higher than the external power supply, voltage VDD in this case. After the charge is transferred, level of the output signal OUT is held to the internal boosting power supply voltage VPP, for example, to 4.6 V via the PMOS transistors TP6, TP7.
COPYRIGHT: (C)1999,JPO
摘要翻译：要解决的问题：为了控制来自内部电压产生电路的高电压供应，以通过用自增压升压电路和电平保持电路形成驱动电路来降低器件的功耗，然后提供电源在驱动具有大幅度的输出节点时的低压外部电源。解决方案：自升压升压电路在低电压外部电源电压VDD（例如3.3 V）工作，并且当输入信号IN从高电平变为低电平时对电容器C1充电。此后，当NMOS晶体管TN15断开，然后节点e变为高电平时，电容器C1的电荷被传送到电平保持电路，并且输出信号输出的电平升高高于外部电源，电压VDD 在这种情况下。在传送电荷之后，输出信号OUT的电平通过PMOS晶体管TP6，TP7被保持到内部升压电源电压VPP，例如达到4.6V。

5. 发明专利

JP2003017591A Semiconductor memory 审中-公开
标题翻译：半导体存储器
公开(公告)号：JP2003017591A
公开(公告)日：2003-01-17
申请号：JP2001202212
申请日：2001-07-03
申请人： Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： NAKAZATO KAZUO , KISU TERUAKI , HASHIMOTO TAKESHI , ITO YUTAKA , MURANAKA MASAYA
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/108 , H01L27/10873 , H01L27/10876
摘要： PROBLEM TO BE SOLVED: To realize a semiconductor storage element suitable for miniaturization and high integration by enabling low voltage operation and enlarging operation margin.
SOLUTION: The gain cell type semiconductor storage element constituting a memory cell of one selection MIS transistor Qt, one writing MIS transistor Qw and one sense MIS transistor Qs and amplifying storage information by the sense MIS transistor Qs constitutes the writing MIS transistor Qw of a vertical structural transistor, it is laminated on the upper part of the sense MIS transistor Qs and the area of a memory cell is contracted by self- matchingly forming the selection MIS transistor Qt on the side.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：通过实现低电压操作和扩大操作裕度，实现适合于小型化和高集成度的半导体存储元件。解决方案：构成一个选择MIS晶体管Qt的存储单元的增益单元型半导体存储元件，一个写入MIS晶体管Qw和一个感测MIS晶体管Qs并且由感测MIS晶体管Qs放大存储信息构成垂直的写入MIS晶体管Qw 结构晶体管，它被层压在感测MIS晶体管Qs的上部，并且通过在侧面自适应地形成选择MIS晶体管Qt来使存储单元的区域收缩。

6. 发明专利

JP2000076896A Semiconductor integrated circuit apparatus 审中-公开
标题翻译：半导体集成电路设备
公开(公告)号：JP2000076896A
公开(公告)日：2000-03-14
申请号：JP24160398
申请日：1998-08-27
申请人： Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： MURANAKA MASAYA , TAKAHASHI AKIRA , ITO YUTAKA , OYAMADA MASAHIRO
IPC分类号： G01R31/28 , G06F12/14 , G06F12/16 , G06F21/24 , G11C11/401 , G11C11/407 , G11C29/00 , G11C29/14
摘要： PROBLEM TO BE SOLVED: To prevent an operation mode from starting wrong and from being set by a third party by making a count operation of a first counter circuit correspond to an input operation for input signals, practically stopping the operation of the first counter circuit when the operations do not coincide and permitting the operation mode by a maximum value output of the counted value.
SOLUTION: A comparing circuit CP compares complementary count signals of non-inversions Q0-Q3 and inversions Q0B-Q3B from a counter circuit CNT with address signals LA0-LA3 and inverting signals LA0B-LA3B from an input circuit INC, and outputs comparison outputs C0-C3. A judging circuit LC1 turns an output signal COIN to a low level when one of the comparison outputs C0-C3 is in an incoincidence state and clears the counter circuit CNT. A logic circuit LC5 counts count outputs of the counter circuit CND, that is, high levels of the non-inversions Q0-Q3 and forms a start signal OPEN when a counted value becomes 1111 in binary notation.
COPYRIGHT: (C)2000,JPO
摘要翻译：要解决的问题：为了防止操作模式从第三方开始错误并由第一计数器电路的计数操作对应于输入信号的输入操作，实际上停止第一计数器电路的操作，当操作不一致并允许操作模式通过计数值的最大值输出。解决方案：比较电路CP将来自计数器电路CNT的非反相Q0-Q3和反相Q0B-Q3B的互补计数信号与来自输入电路INC的地址信号LA0-LA3和反相信号LA0B-LA3B进行比较，并输出比较输出C0 -C3。当比较输出C0-C3中的一个处于不一致状态时，判断电路LC1使输出信号COIN变为低电平，并清除计数器电路CNT。逻辑电路LC5对计数器电路CND的计数输出进行计数，即非反相Q0-Q3的高电平，并且当以二进制符号计数值变为1111时，逻辑电路LC5形成起始信号OPEN。

7. 发明专利

JPH11273347A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路设备
公开(公告)号：JPH11273347A
公开(公告)日：1999-10-08
申请号：JP7054598
申请日：1998-03-19
申请人： Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： MURANAKA MASAYA
IPC分类号： G11C11/409 , G11C11/407
摘要： PROBLEM TO BE SOLVED: To obtain a semiconductor integrated circuit device whose power consumption is reduced sharply, whose circuit constitution is simple and in which a voltage level is converted stably.
SOLUTION: In level conversion circuits 17 to 19 which convert the level of a data signal in a data input buffer or the like, an input signal DIN is changed to a signal Lo from a signal Hi. Then, a transistor T1 and a transistor T4 are turned off, a transistor T2 and a transistor T3 are turned on, and an electric charge which is stored in a capacitor C is output via the transistor T2. After that, an output signal DOUT is held by a voltage-drop power supply VDL via the transistor T3. Thereby, since the load of the output signal DOUT ca be supplemented with a power supply voltage VCC, the supply capacity of the voltage drop power supply VDL can be reduced, and the power consumption of a semiconductor integrated circuit device can be reduced sharply.
COPYRIGHT: (C)1999,JPO
摘要翻译：要解决的问题：为了获得电力消耗急剧下降的半导体集成电路器件，其电路结构简单并且稳定地转换电压电平。解决方案：在转换数据输入缓冲器等中的数据信号的电平的电平转换电路17至19中，输入信号DIN从信号Hi改变为信号Lo。然后，晶体管T1和晶体管T4截止，晶体管T2和晶体管T3导通，并且经由晶体管T2输出存储在电容器C中的电荷。之后，输出信号DOUT由电压降电源VDL通过晶体管T3保持。因此，由于输出信号DOUT的负载可以补充电源电压VCC，所以可以降低电压降电源VDL的供应容量，并且可以急剧减少半导体集成电路器件的功耗。

8. 发明专利

JP2002269976A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JP2002269976A
公开(公告)日：2002-09-20
申请号：JP2001066444
申请日：2001-03-09
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： ITO YUTAKA , MURANAKA MASAYA
IPC分类号： G11C11/402 , G11C11/405 , H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To satisfy interchangeability of DRAMs in a semiconductor memory including a gain cell. SOLUTION: When a memory cell is constituted of a first transistor (101) conducted in accordance with a voltage level of a word line (WL) and a second transistor (102) which holds information-voltage transmitted from a data line through the first transistor while which can output information based on the information voltage, the second transistor is made a source follower. Thereby, as read-out information to a data line coincides with a logical value in the case of write-in for the storage node, write-in for the storage node can be performed again as it is, and interchangeability of the DRAMs is satisfied.

9. 发明专利

JPH06333392A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH06333392A
公开(公告)日：1994-12-02
申请号：JP11813293
申请日：1993-05-20
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUZUKI YUKIE , NAKAI KIYOSHI , MURANAKA MASAYA
IPC分类号： G11C11/409 , G11C11/401
摘要： PURPOSE:To suppress the influence of decreasing a power source voltage affecting the margin of reading operation and an access time and to enhance the voltage lowering of a dynamic RAM, etc. CONSTITUTION:The effective level of a pre-charging control signal PCSO supplied to the gate of a pre-charging MOSFET N9 is made to be a high voltage VCH immediately after a dynamic RAM is made a non-selection state from its selection state so as to make the corresponding memory array an active state and made to become the power source voltage VCC during the period in which the corresponding memory array is made the active state after the dynamic RAM is again made the selection state. At the beginning of the non- selection state of the dynamic RAM, the voltage between the gate and the source of the MOSFET N9 is increased and the equalizing operation of a complementary bit line is surely performed at high speed. During the period in which the corresponding memory array is made the active state after the dynamic RAM is again made the selection state, the potential of the pre-charging control signal is lowered earlier down to the power source voltage VCC and the MOSFET N9 is quickly turned off.

10. 发明专利

JPH03205698A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH03205698A
公开(公告)日：1991-09-09
申请号：JP55790
申请日：1990-01-08
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MURANAKA MASAYA
IPC分类号： G11C29/00 , G11C11/401 , G11C29/04 , H01L21/82 , H01L27/10
摘要： PURPOSE:To stably and surely decide whether a defect is relieved or not by reversing the direction of the current change of an external terminal between the redudancy relief state and the redundancy non-relief state in response to the control of switching from the first operation mode to the second operation mode. CONSTITUTION:When a control signal phiren is in the low level, a control signal phisig is first in the low level and is changed to the high level. When the relief signal, namely, the control signal phiren is in the high level, the control signal phisig is first in the high level and is changed to the low level. Consequently, the direction of the current change of a data input/output terminal 10 is reversed between the redundancy relief state and the redundancy non-relief state in response to switching from the normal mode to the test mode when the operation mode is first set to the normal mode and is switched to the test mode at the time of applying a prescribed voltage higher than a supply voltage Vdd to the data input/output terminal 10. Thus, it is stably and surely decided whether a defect is relieved by redundancy or not.

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