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1. 发明专利

JP2003037249A Semiconductor integrated circuit device 审中-公开
标题翻译：半导体集成电路设备
公开(公告)号：JP2003037249A
公开(公告)日：2003-02-07
申请号：JP2001221931
申请日：2001-07-23
申请人： Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： KUBOTA KISHIYO , HASHIMOTO TAKESHI
IPC分类号： G11C14/00 , G11C11/402 , G11C16/04 , H01L27/10 , H01L27/108
CPC分类号： G11C16/0433 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To accelerate a memory read operation which is constituted using a PLED transistor. SOLUTION: A shunt line L, grounded at both ends and electrically connected to a source power line GND, is inserted in a direction orthogonal to the source power line GND of a MISFET Tr1 and noise (potential) surfacing in the source power line GND is released to the ground potential. By releasing the noise surfacing in the source power line GND to the ground potential, reduction of the voltage between the source and drain of the MISFET Tr1 is suppressed.
摘要翻译：要解决的问题：加速使用PLED晶体管构成的存储器读取操作。解决方案：在与MISFET Tr1的源极电源线GND正交的方向上插入在两端接地并电连接到源极电源线GND的分路线L，并且源极电源线GND中的噪声（电位）释放到地下潜力。通过将源极电源线GND中的噪声表面释放到接地电位，可以抑制MISFET Tr1的源极和漏极之间的电压的降低。

2. 发明专利

JP2005018954A Plate voltage occurrence circuit 有权
标题翻译：电压电压电路
公开(公告)号：JP2005018954A
公开(公告)日：2005-01-20
申请号：JP2003186499
申请日：2003-06-30
申请人： Elpida Memory Inc , Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： HASHIMOTO TAKESHI , KOJIMA HIROMITSU
IPC分类号： H03K19/094 , G11C5/14 , G11C11/404 , G11C11/406 , G11C11/407 , G11C11/4074 , H03K19/0948
CPC分类号： G11C5/147 , G11C11/406 , G11C11/4074 , G11C2211/4016
摘要： PROBLEM TO BE SOLVED: To provide the characteristics of a conventional plate voltage generation circuit, to optionally control a plurality of dead zones even during a chip operation even with a single reference voltage, and to reduce a layout area only by adding a few elements to the conventional circuit.
SOLUTION: Dead zone control circuits 12a and 12b are added to conventional differential circuits 11a and 11b for generating plate voltages and a push-pull output circuit 3. Dead zone control signals (a) and (b) are supplied from the outside to the dead zone control circuits 12a and 12b to set dead zone widths. The dead zone control circuit 12a is connected in parallel to one transistor M9 of two making the differential pair of the differential circuit 11a, an output corresponding to the transistor M9 is controlled by the H (high level) signal of the dead zone control signal (a), and the dead zone width is enlarged. The dead zone control circuit 12b side has the same function, and is capable of changing the dead zone width by changing the setting of the dead zone control signal.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了提供常规板电压产生电路的特性，即使在单个参考电压下甚至在芯片操作期间也可以控制多个死区，并且仅通过添加一个传统电路的元素很少。解决方案：将死区控制电路12a和12b添加到用于产生板电压的常规差分电路11a和11b以及推挽输出电路3.死区控制信号（a）和（b）从外部提供到死区控制电路12a和12b以设定死区宽度。死区控制电路12a并联连接到两个差分电路11a的差分对的一个晶体管M9，对应于晶体管M9的输出由死区控制信号的H（高电平）信号控制 a），死区宽度扩大。死区控制电路12b侧具有相同的功能，并且能够通过改变死区控制信号的设置来改变死区宽度。版权所有（C）2005，JPO＆NCIPI

3. 发明专利

JP2003017591A Semiconductor memory 审中-公开
标题翻译：半导体存储器
公开(公告)号：JP2003017591A
公开(公告)日：2003-01-17
申请号：JP2001202212
申请日：2001-07-03
申请人： Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： NAKAZATO KAZUO , KISU TERUAKI , HASHIMOTO TAKESHI , ITO YUTAKA , MURANAKA MASAYA
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/108 , H01L27/10873 , H01L27/10876
摘要： PROBLEM TO BE SOLVED: To realize a semiconductor storage element suitable for miniaturization and high integration by enabling low voltage operation and enlarging operation margin.
SOLUTION: The gain cell type semiconductor storage element constituting a memory cell of one selection MIS transistor Qt, one writing MIS transistor Qw and one sense MIS transistor Qs and amplifying storage information by the sense MIS transistor Qs constitutes the writing MIS transistor Qw of a vertical structural transistor, it is laminated on the upper part of the sense MIS transistor Qs and the area of a memory cell is contracted by self- matchingly forming the selection MIS transistor Qt on the side.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：通过实现低电压操作和扩大操作裕度，实现适合于小型化和高集成度的半导体存储元件。解决方案：构成一个选择MIS晶体管Qt的存储单元的增益单元型半导体存储元件，一个写入MIS晶体管Qw和一个感测MIS晶体管Qs并且由感测MIS晶体管Qs放大存储信息构成垂直的写入MIS晶体管Qw 结构晶体管，它被层压在感测MIS晶体管Qs的上部，并且通过在侧面自适应地形成选择MIS晶体管Qt来使存储单元的区域收缩。

4. 发明专利

JP2003068076A Power control method for semiconductor memory, and semiconductor memory 审中-公开
标题翻译：半导体存储器的功率控制方法和半导体存储器
公开(公告)号：JP2003068076A
公开(公告)日：2003-03-07
申请号：JP2001256913
申请日：2001-08-27
申请人： Elpida Memory Inc , Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： NAKAI KIYOSHI , ITO YUTAKA , HASHIMOTO TAKESHI , KATO HIDEAKI
IPC分类号： G11C11/407 , G11C7/10 , G11C11/401 , G11C11/403 , G11C11/406 , G11C11/4074 , G11C29/42 , G11C29/00
CPC分类号： G11C7/1018 , G11C11/406 , G11C2207/2227
摘要： PROBLEM TO BE SOLVED: To greatly reduce power consumption while being in a standby state. SOLUTION: A power control method for this semiconductor memory is provided with a super low power consumption mode by which power control is performed in a standby state, this super low power consumption mode includes a burst/self-refresh state BSST, a power-off state PFST, and a power on state PNST, in the burst/self-refresh state BSST, memory cells are refreshed concentrically, in the power off state PFST, internal power source circuits are turned off partially, in the power-on state, the internal power source circuits turned off partially are turned on.
摘要翻译：要解决的问题：在待机状态下大大降低功耗。解决方案：该半导体存储器的功率控制方法具有在待机状态下进行功率控制的超低功耗模式，该超低功耗模式包括突发/自刷新状态BSST，断电状态PFST和上电状态PNST，在脉冲串/自刷新状态BSST中，存储器单元同心地刷新，在断电状态PFST中，内部电源电路部分地被断开，处于通电状态，部分断开的内部电源电路接通。

5. 发明专利

JP2006004558A Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：JP2006004558A
公开(公告)日：2006-01-05
申请号：JP2004181735
申请日：2004-06-18
申请人： Elpida Memory Inc , Hitachi Ulsi Systems Co Ltd , エルピーダメモリ株式会社 , 株式会社日立超エル・エス・アイ・システムズ
发明人： ITO YUTAKA , HASHIMOTO TAKESHI , YAMAZAKI EIJI , TAKEUCHI SHIGEO , KANEDA MASAYUKI
IPC分类号： G11C11/401 , G11C7/00 , G11C11/403 , G11C11/406
CPC分类号： G11C11/406 , G11C2211/4062 , G11C2211/4067
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor storage device permitting the entry with no wait, when the entry into a data holding operational mode of a super low power consumption is performed again.
SOLUTION: In the semiconductor storage device in which an ECC circuit is mounted on-chip, the data holding operational mode shifts to an idle state IST, when receiving an instruction for the exit from the data holding operational mode, in an encoded state EEST in which an ECC encoding circuit adds parity information to the data of memory cells and stores them, a burst self refresh state BSST in which a concentrated refresh operation of the memory cells is performed, a power off state PFST in which an internal power supply circuit is partially turned off, a power on state PNST in which the internal power supply circuit that is partially turned off is turned on, the decoding state EDST in which a decoding circuit for the error detection/correction corrects the error of the memory cell, and the encoded state, in the order of the state transition. The reentry from the decoded state EDST to the BSST can be permitted.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了提供允许进入等候的半导体存储装置，当再次执行进入超低功耗的数据保持操作模式时。解决方案：在其中ECC电路安装在片上的半导体存储装置中，数据保持操作模式在接收到从数据保持操作模式退出的指令时转移到空闲状态IST 状态EEST，其中ECC编码电路将奇偶校验信息添加到存储器单元的数据并将其存储，执行存储单元的集中刷新操作的突发自刷新状态BSST，其中内部功率供电电路部分关闭，部分关闭的内部电源电路接通的电源接通状态PNST，其中用于错误检测/校正的解码电路校正存储器单元的错误的解码状态EDST ，和编码状态，按照状态转换的顺序。可以允许从解码状态EDST到BSST的再入。版权所有（C）2006，JPO＆NCIPI

6. 发明专利

JP2006004546A Control method for refresh counter circuit and refresh operation 有权
标题翻译：刷新计数器电路和刷新操作的控制方法
公开(公告)号：JP2006004546A
公开(公告)日：2006-01-05
申请号：JP2004181453
申请日：2004-06-18
申请人： Elpida Memory Inc , Hitachi Ulsi Systems Co Ltd , エルピーダメモリ株式会社 , 株式会社日立超エル・エス・アイ・システムズ
发明人： KANEDA MASAYUKI , HASHIMOTO TAKESHI
IPC分类号： G11C11/406
CPC分类号： G11C11/406 , G11C2211/4062
摘要： PROBLEM TO BE SOLVED: To provide a refresh counter circuit, and the like, which, in performing refresh operation for both a normal area and a parity area, prevents failure in operation and suitable for lower power consumption. SOLUTION: At the time of the refresh operation of a memory device having both the normal area and the parity area in the refresh counter circuit, counters X0-X12 correspond to address space of the normal area, counters X0-X3, X9-X12 correspond to the address space of the parity area, a counter X13 for generating row addresses for both of them and for generating the area decision signal for deciding the count operation for either the normal area or the parity area is arranged. And, by controlling for switching path switches 31-34, the refresh operation is performed while switching the normal area and the parity area. When stop for the refresh operation for the parity area is instructed before the operation is completed, an auto reset circuit 40 generates a reset signal for resetting into a state where the count operation for the normal area is decided by an area decision signal and supplies it to the counter X13. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供在正常区域和奇偶校验区域进行刷新操作时防止操作失败并适合于较低功耗的刷新计数器电路等。解决方案：在刷新计数器电路中具有正常区域和奇偶校验区域的存储器件的刷新操作时，计数器X0-X12对应于法线区域的地址空间，计数器X0-X3，X9 -X12对应于奇偶校验区域的地址空间，用于产生用于它们的行地址的计数器X13和用于生成用于判定正常区域或奇偶校验区域的计数操作的区域判定信号。并且，通过控制切换路径开关31-34，在切换正常区域和奇偶校验区域的同时执行刷新操作。当在操作完成之前指示用于奇偶校验区域的刷新操作的停止时，自动复位电路40产生用于复位的复位信号，使其为通过区域判定信号决定正常区域的计数操作的状态，并将其提供到柜台X13。版权所有（C）2006，JPO＆NCIPI

7. 发明专利

JP2006031312A Storage device 有权
标题翻译：储存设备
公开(公告)号：JP2006031312A
公开(公告)日：2006-02-02
申请号：JP2004208105
申请日：2004-07-15
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： TAKADA YUTAKA , KOBAYASHI NAOTAKA , HASHIMOTO TAKESHI , HASHIMOTO AKIYOSHI , NAKAYAMA SHINICHI
IPC分类号： G06F11/00 , G06F3/06
CPC分类号： G06F8/67 , G06F8/665
摘要： PROBLEM TO BE SOLVED: To provide a technique capable of updating firmware while continuing services for clients, regarding a circuit board that configures a controller of a storage device. SOLUTION: A plurality of blades 10 that configures the controller 100 has an old BIOS 20 on a flash memory 15. A cluster comprises the blades 10 whose firmware is to be updated. During the update of the firmware, a process unit is executed on the board to be updated, the process unit including a process by which services provided by the OS 21 of the blade 10 for the firmware update are shifted to the OS 21 of another blade 10 within the cluster and a firmware update process by which the old BIOS 20 of the blade 10 no longer providing the services is updated using a BIOS update program 22 and a new BIOS image 23. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：关于配置存储设备的控制器的电路板，提供能够在为客户端持续服务的同时更新固件的技术。解决方案：配置控制器100的多个刀片10在闪存15上具有旧的BIOS 20.集群包括其固件将被更新的刀片10。在更新固件期间，在要更新的板上执行处理单元，处理单元包括由用于固件更新的刀片10的OS 21提供的服务被移动到另一个刀片的OS 21的处理并且使用BIOS更新程序22和新的BIOS映像23更新刀片10的旧BIOS 20不再提供服务的固件更新过程。（C）2006年，JPO和NCIPI

8. 发明专利

JP2003068883A Semiconductor storage device 审中-公开
标题翻译：半导体存储设备
公开(公告)号：JP2003068883A
公开(公告)日：2003-03-07
申请号：JP2001255202
申请日：2001-08-24
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： HASHIMOTO TAKESHI , IWAI HIDETOSHI
IPC分类号： H01L21/8242 , H01L21/8244 , H01L27/108 , H01L27/11
CPC分类号： H01L27/11 , H01L27/1104
摘要： PROBLEM TO BE SOLVED: To reduce a memory cell size of an SRAM.
SOLUTION: The memory cell of the SRAM has a transfer MISFET, a drive MISFET and a load MISFET in such a manner that the load MISFET is formed on an upper part of the drive MISFET. The load MISFET has a vertical structure in which a gate electrode 23 is disposed on a side face of a laminated structure P extended in the direction perpendicular to a main surface of a semiconductor substrate 1 via a gate insulating film 22. The structure P has a polycrystal silicon film in which a lower semiconductor layer 13, an intermediate semiconductor layer 14 and an upper semiconductor layer 15 are sequentially laminated in the order from the lower layer.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：减少SRAM的存储单元大小。解决方案：SRAM的存储单元具有传输MISFET，驱动MISFET和负载MISFET，使负载MISFET形成在驱动MISFET的上部。负载MISFET具有垂直结构，其中栅电极23设置在经由栅极绝缘膜22在垂直于半导体衬底1的主表面的方向延伸的层叠结构P的侧面上。结构P具有其中下半导体层13，中间半导体层14和上半导体层15按照从下层顺序层叠的多晶硅膜。

9. 发明专利

JP2000048598A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JP2000048598A
公开(公告)日：2000-02-18
申请号：JP21636098
申请日：1998-07-31
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： MURANAKA MASAYA , ITO YUTAKA , OYAMADA MASAHIRO , TAKAHASHI AKIRA , HASHIMOTO TAKESHI
IPC分类号： G11C11/413 , G11C11/401 , G11C11/407 , G11C11/408 , G11C11/409 , G11C29/00 , G11C29/50 , H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To realize high performance and efficient sorting test through a simple arrangement by providing a unit for forming an inner voltage different from a first voltage by receiving first and second voltages from first and second external terminals and altering the inner voltage to a voltage different from normal operation for an internal power supply circuit. SOLUTION: A first reference voltage for normal operation is fed to a voltage follower circuit comprising a P channel output MOSFET 38 and an operating circuit 37 through an MOSFET 35 being switched by a control signal NOR at the time of normal operation. Similarly, second and third reference voltages are fed to the voltage follower circuit and inner voltage drop VDL is switched by selecting one of first through reference voltages. Defect is detected even for a circuit operating normally with a voltage of strict operational conditions. In case of a defect of short period principally caused by inner voltage drop VDL, the defect can be detected by lowering the inner voltage drop VDL.

10. 发明专利

JP2000030443A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JP2000030443A
公开(公告)日：2000-01-28
申请号：JP20161198
申请日：1998-07-16
申请人： HITACHI LTD
发明人： HASHIMOTO TAKESHI , NAKAI KIYOSHI , IWAI HIDETOSHI
IPC分类号： G11C11/407 , G11C11/408 , G11C11/409
摘要： PROBLEM TO BE SOLVED: To increase operation speed, to reduce a manufacturing cost, and to reduce power consumption of a dynamic type RAM and the like in which a sub-threshold current reducing system is adopted. SOLUTION: When Dynamic type RAM and the like are shifted to an active state from a standby state, a sub-threshold current reducing system is not applied to row group circuits such as a X address buffer XB, an X address decoder XD, and the like which start operation at a comparatively early time, but a sub-threshold current reducing system is applied only to column group circuits including a Y address buffer YB and a Y address decoder YD, data input/output circuit IO, and the like which start operation at a comparatively late time.

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