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1. 发明专利

JP2000077608A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2000077608A
公开(公告)日：2000-03-14
申请号：JP24300798
申请日：1998-08-28
申请人： Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： NAKAMURA ATSUSHI , KATAGIRI MITSUAKI , YOKOMIZO KOICHI , NAKAUCHI ATSUHIKO , TOTANI TATSURO , SHIMIZU HIROYA , SHIRAKAWA SHINJI , IWABUCHI MASARU
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/822 , H01L27/00 , H01L27/04
CPC分类号： H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of realizing a sufficient EMI(electromagnetic wave interference) countermeasure by a method wherein a dropped voltage is stabilized and further a noise propagation to an external part is reduced in a circuit structure integral with an inner voltage drop circuit. SOLUTION: This semiconductor device is a microcomputer in which a power source voltage VCC supplied from an external part is dropped by an inner voltage drop circuit VCLG, and an inner circuit is driven by use of a dropped voltage VCL lower than the power source voltage VCC, and in order to stabilize the dropped voltage VCL, in an external part of an LSI package containing an LSI chip of the microcomputer, a capacitor C10 is attached externally between an external terminal of the dropping voltage VCL and an external terminal of a ground voltage VSS. Furthermore, in order to reduce a noise propagation to an external part, an inductance component comprising a high inductance element, wiring, a wiring lead, and the like is imparted to the power source voltage VCC.
摘要翻译：要解决的问题：提供一种半导体器件，其能够通过一种方法实现足够的EMI（电磁波干扰）对策，其中降低的电压稳定，并且进一步减小与外部部分的噪声传播的电路结构与内部降压电路。解决方案：该半导体器件是其中由外部部分提供的电源电压VCC由内部电压降电路VCLG掉下的微型计算机，并且通过使用低于电源电压VCC的下降电压VCL来驱动内部电路并且为了稳定下降电压VCL，在包含微计算机的LSI芯片的LSI封装的外部部分中，电容器C10外部附接在滴电压VCL的外部端子与接地电压的外部端子之间 VSS。此外，为了减少对外部的噪声传播，对电源电压VCC赋予包括高电感元件，布线，布线引线等的电感成分。

2. 发明专利

JPS6223131A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS6223131A
公开(公告)日：1987-01-31
申请号：JP16194785
申请日：1985-07-24
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： NAKAUCHI ATSUHIKO
IPC分类号： H01L27/092 , H01L21/3205 , H01L21/82 , H01L21/8238 , H01L23/52 , H01L27/118
摘要： PURPOSE:To lower power consumption by a method wherein an unnecessary current route is eliminated from between a power source voltage wiring and reference voltage wiring. CONSTITUTION:The gate electrode 9 of a unit cell 4A in some cases out of use is connected to a reference voltage Vss (or to a power source voltage Vcc) that is a fixed voltage source. A signal-outputting wiring 16, connecting semiconductor regions 10 and 11 that are to serve as drains for MISFET Qp and Qn, is intentionally disconnected for the establishment of electrical isolation between the semiconductor regions 10 and 11. With the isolation established, there will be no unnecessary current route between the reference voltage Vss wiring and source voltage Vcc wiring, even in the presence of a minor defect 1 in a P-N junction between the semiconductor region 11 and a well region 7A. That is, between the well region 7A supplied with the reference voltage Vss and signal outputting wiring 16 supplied with the power source voltage Vcc, there will be no electric current route that may otherwise be constituted of the semiconductor region 11, signal outputting wiring 16, and p-channel MISFET Qp. This reduces the power consumption of the unit cell 4A not in use.

3. 发明专利

JPS6481406A PULSE GENERATING CIRCUIT 失效
公开(公告)号：JPS6481406A
公开(公告)日：1989-03-27
申请号：JP23723787
申请日：1987-09-24
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： NAKAUCHI ATSUHIKO
IPC分类号： H03K3/017
摘要： PURPOSE:To generate pulses having optional pulse duty corresponding to a bit pattern by generating a digital signal having the bit pattern corresponding to the pulse duty and supplying it to a shift register in parallel, and outputting it in series according to the clock pulses. CONSTITUTION:The bit patterns of digital input signals B1-Bn are outputted in the order of the bits Bn-B1 in series according to the transferring operation of the shift register. The pulse signals corresponding to the bit patterns are therefore outputted. For example, when the B1-Bn consist of four bits and are 1100, pulses with 50% pulse duty like 0011 are outputted from the output terminal OUT of the shift register. Consequently, the (n)-bit shift register consisting of flip-flop circuits FF1-FFn generates pulses with (n-1) kinds of pulse duty from 1/n to (n-1)/n optionally.

4. 发明专利

JPS5877319A LEVEL CONVERTING CIRCUIT 失效
公开(公告)号：JPS5877319A
公开(公告)日：1983-05-10
申请号：JP17459281
申请日：1981-11-02
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： KOBAYASHI HATSUHIKO , NAKAUCHI ATSUHIKO , ABE HIROYUKI
IPC分类号： H03K5/02 , H03K19/0185
摘要： PURPOSE:To constitute a level converting circuit where its output has sufficient amplitude with two MOSFETs, by decreasing the effect of the substrate effect through the forming of the MOSFETs on independent substrates, respectively. CONSTITUTION:Two N-channel MOSFETs Q1, Q2 are connected in series, the drain of the FETQ1 is connected to a power supply voltage VDD and the source of the FETQ2 to a power supply voltage VEE. The MOSFETs Q1 and Q2 are formed on independent substrates, respectively. That is, the MOSFETs Q1, Q2 are electrically isolated with each other, by forming them on substrates of P-well isolated on one silicon semiconductor substrate.

5. 发明专利

JPH02310947A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH02310947A
公开(公告)日：1990-12-26
申请号：JP13138789
申请日：1989-05-26
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： KII YOSHIO , NAKAUCHI ATSUHIKO
IPC分类号： H01L27/04 , G06F1/12 , H01L21/82 , H01L21/822 , H03K19/003
摘要： PURPOSE:To increase a strength against a noise of an input terminal and to prevent a malfunction of a system by installing the following: a delay circuit between an input terminal of an LSI and an internal logic circuit; a logic gate whose inputs are an an output signal of the delay circuit and the input of the input terminal. CONSTITUTION:For example, three delay circuits 2a, 2b, 2c whose delay time is different from one another and one AND gate 3 corresponding to an input terminal 1 are provided. When a pulse width p2 of a signal (a) supplied to the input terminal 1 is shorter than a delay time td1 of the delay circuit 2a, the input signal (a) is set to a low level before an output signal (b) of the delay circuit 2a is changed to a high level; as a result, an output signal (c) of the AND gate 3 remains at the low level and is not changed. Thereby, a signal whose pulse width is shorter than the delay time td1 is regarded as a noise and is restrained from being transmitted to an internal logic circuit.

6. 发明专利

JPS5877318A LEVEL CONVERTING CIRCUIT 失效
公开(公告)号：JPS5877318A
公开(公告)日：1983-05-10
申请号：JP17459181
申请日：1981-11-02
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： KOBAYASHI HATSUHIKO , NAKAUCHI ATSUHIKO
IPC分类号： H03K5/02 , H03K19/00 , H03K19/0185
摘要： PURPOSE:To arbitrarily select an output level regardless of constant power supply potential, by adjusting the increment of a threshold voltage due to a substrate effect of MOSFETs to a certain value in response to the power supply voltage and the desired output level. CONSTITUTION:MOSFETs Q1, Q2 are formed on separate substrates provided on one substrate separately. Signals inputted to the gate of the MOSFETs Q1, Q2 have amplitude of VEE-VGND and phases shifted by 180 deg. each other. The amplitude VEE-VGND of the input signals is converted into the amplitude of VEE-VDD1. The increment of the threshold voltage because of the substrate effect can be adjusted through the change in the size and the substrate potential of the MOSFETQ1, and the level of an output signal VD is selectively set to an arbitrary level between the VEE-VDD.

7. 发明专利

JPH09130166A CMOS DIFFERENTIAL AMPLIFIER CIRCUIT 失效
公开(公告)号：JPH09130166A
公开(公告)日：1997-05-16
申请号：JP27909495
申请日：1995-10-26
申请人： HITACHI LTD , HITACHI MICROCOMPUTER SYST
发明人： NACHI SHIKIKO , YAMAMOTO MOROHISA , NAKAUCHI ATSUHIKO , SUGANUMA MASANORI
IPC分类号： H03F3/45
摘要： PROBLEM TO BE SOLVED: To reduce the changes of both gain and phase frequency characteristics and to secure the satisfactory DG(differential gain) and DP(differential phase) characteristics by regulating the larger one of both currents amplified by a 1st or 3rd current mirror circuit by the other smaller current. SOLUTION: When a pair of input signals V (+) and V (-) are set at the same level, the voltage of the same level as these input signals is outputted to an output terminal OUT. If the potential of the signal V (+) rises under such conditions, the current I1 flowing to a MOS transistor TR MN9 increases and the current I2 flowing to a TR MN10 reduces. Therefore, the gate voltage of a MOS TR MP7 placed at the output side of a 1st current mirror circuit 23 rises to try to increase the drain current of the TR MP7. Thus the on- resistance of the TR MP7 reduces. Then the gate voltage of a MOS TR MN13 of a 3rd current mirror circuit 24 drops to try to reduce the drain current of the TR MN13. Thus the on-resistance of the TR MN13 increases. As a result, the output voltage rises.

8. 发明专利

JPH06244367A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH06244367A
公开(公告)日：1994-09-02
申请号：JP2951193
申请日：1993-02-19
申请人： HITACHI LTD , HITACHI MICOM SYST KK
发明人： YAMADA NOBUAKI , ARAI TOMOYUKI , NAKAUCHI ATSUHIKO
IPC分类号： H01L21/8234 , H01L27/088
摘要： PURPOSE:To provide a semiconductor integrated circuit device in which the area of lines can be freely designed by the addition of an additional capacity area, in a MOS.LSI having a diffusion layer on-the-line polysilicon lines. CONSTITUTION:A semiconductor integrated circuit device has CMOS inverter output L-layer.on-the-line polysilicon lines. In this device, a LOCOS 2, a gate oxide film 3, gates and lines made of polysilicon 4, an n-type L layer 5, an insulation film 6 made of PSG, lines such as Vcc and GND made of AL 7, are formed in that order on a p-type semiconductor substrate 1. An additional capacity 8 is added to a line output section (OUT) made of polysilicon 4 in such a way that a ratio of the area of polysilicon/(the area of a parasitic capacity+the area of the additional capacity) is below 30.

9. 发明专利

JPS5877330A TRI-STATE CIRCUIT 失效
公开(公告)号：JPS5877330A
公开(公告)日：1983-05-10
申请号：JP17459381
申请日：1981-11-02
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： KOBAYASHI HATSUHIKO , NAKAUCHI ATSUHIKO , KONNO HARUTSUGU , ABE HIROYUKI
IPC分类号： H03K19/0175 , H03K19/094 , H03K19/0948
摘要： PURPOSE:To decrease the occupied area of a prebuffer and the chip size, by reducing the number of components of the prebuffer to directly drive an MOSFET consisting of an output buffer. CONSTITUTION:An output buffer 1 consists of an N channel MOSFETQ1 and a P channel MOSFETQ2. An NAND gate 2 is a gate as a prebuffer, to which a control signal Pc and a data signal Pd are inputted. Further, an inverter 5 is a prebuffer to drive the MOSFETQ2. The inverter 5 inverts the logical output of an NAND gate 6 taking the control signal Pc and the output of the NAND gate 2 as inputs and outputs them to the MOSFETQ2.

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