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1. 发明专利

JPS59210587A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：JPS59210587A
公开(公告)日：1984-11-29
申请号：JP8274483
申请日：1983-05-13
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： KII YOSHIO , IWATA KATSUMI , FUNATSU KENZOU , HOTSUTA SHINKICHI
IPC分类号： G11C11/417 , G11C11/34
CPC分类号： G11C11/34
摘要： PURPOSE:To reduce current consumption of a built-in RAM and reduce current consumption of the whole LSI in an LSI provided with an RAM by forming the precharge signal of a data line basing on an access signal. CONSTITUTION:MOSFETs Q11-Q14 for precharging are provided in data lines D, D'. Precharge signal phiP is formed basing on an RAM access signal AC outputted from an RAM I/O and a system clock CK, and precharge MOSFETs Q11-Q14 on the data line are turned on by a Y decoder 3. Consequently, the data line in the RAM is precharged only at the time of accessing, and at the same time, precharging is performed only for selected data line. Thus, current consumption is reduced remarkably.
摘要翻译：目的：通过基于访问信号形成数据线的预充电信号，减少内置RAM的电流消耗，并降低设置在RAM的LSI中的整体LSI的电流消耗。构成：在数据线D，D'中提供用于预充电的MOSFET Q11-Q14。预充电信号phiP基于从RAM I / O和系统时钟CK输出的RAM访问信号AC形成，数据线上的预充电MOSFET Q11-Q14由Y解码器3导通。因此，数据线 RAM仅在访问时被预充电，并且同时仅对选择的数据线执行预充电。因此，电流消耗显着降低。

2. 发明专利

JPS59218569A Microcomputer 失效
标题翻译：微机
公开(公告)号：JPS59218569A
公开(公告)日：1984-12-08
申请号：JP9237583
申请日：1983-05-27
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： OGAWA HIROMASA , HOTSUTA SHINKICHI , IWATA KATSUMI , FUNATSU KENZOU
IPC分类号： G06F9/48 , G06F9/06 , G06F15/78
摘要： PURPOSE: To execute the designation of a computer control area by an operation from the outside, by constituting so that the contents of an address counter for designating an address of a memory in which a program is stored can be set directly from the outside.
CONSTITUTION: The parallel set input of a program counter PC is connected to a data bus DB through a bus changeover switch S1. This data bus changeover switch S1 is controlled by a control signal C1 from a flip-flop. When an interrupting signal INT is applied from the outside, the data bus DB of the input/ output port I/O side is switched to the parallel set input side of the program counter PC, In this case, when a data is loaded on the data bus DB of the inside, this data is set directly to the program counter PC.
COPYRIGHT: (C)1984,JPO&Japio
摘要翻译：目的：通过构成使得能够从外部直接设定用于指定存储程序的存储器的地址的地址计数器的内容来执行计算机控制区域的指定。构成：程序计数器PC的并行输入通过总线切换开关S1连接到数据总线DB。该数据总线切换开关S1由来自触发器的控制信号C1控制。当从外部施加中断信号INT时，输入/输出端口I / O侧的数据总线DB被切换到程序计数器PC的并行设置输入侧。在这种情况下，当数据被加载到数据总线DB内部，这个数据直接设置在程序计数器PC上。

3. 发明专利

JPS59218561A Microcomputer 失效
标题翻译：微机
公开(公告)号：JPS59218561A
公开(公告)日：1984-12-08
申请号：JP9237383
申请日：1983-05-27
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： OGAWA HIROMASA , KII YOSHIO , FUNATSU KENZOU , IWATA KATSUMI
IPC分类号： G06F9/48 , G06F9/46 , G06F15/78
摘要： PURPOSE: To raise the degree of freedom of a program design by deciding a priority order of an interruption by a software, so that the priority order of plural interruptions can be set and changed freely and easily by a user side.
CONSTITUTION: Interruption request signals I
1 WI
4 are inputted to holding circuits F
2 WF
4 , respectively, and held. An interruption priority control means PID is interposed between the holding circuits F
1 WF
4 and interruption inputs P
1 W P
4 . This interruption priority control means PID is constituted of a kind of decoder consisting of a logical gate array. This control means PID is constituted so that a combination of a corresponding relation of the holding circuits F
1 WF
4 and the interruption inputs P
1 WP
4 can be optionally changed.
COPYRIGHT: (C)1984,JPO&Japio
摘要翻译：目的：通过确定软件中断的优先顺序来提高程序设计的自由度，使用户可以自由设置多个中断的优先顺序。构成：中断请求信号I1-I4分别输入到保持电路F2-F4并保持。在保持电路F1-F4和中断输入P1-4 P4之间插入有中断优先控制装置PID。该中断优先级控制装置PID由由逻辑门阵列组成的解码器的种类构成。该控制装置PID构成为可以可选地改变保持电路F1-F4和中断输入P1-P4的对应关系的组合。

4. 发明专利

JPS6011942A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS6011942A
公开(公告)日：1985-01-22
申请号：JP11830883
申请日：1983-07-01
申请人： HITACHI LTD
发明人： FUNATSU KENZOU , HOTSUTA SHINKICHI
IPC分类号： G06F11/22 , G06F11/267
摘要： PURPOSE:To prevent assuredly the generation of trouble through the appropriate evaluation by using external devices different in level of working power supply voltage directly for evaluation. CONSTITUTION:A level conversion circuit 22 is set between an ROM interface 20 and an EP-ROM14 of a semiconductor IC device 10 for evaluation. Thus a direct access is possible to the EP-ROM14 of a comparatively high signal level although the signal level is kept low for a data processor 12 of the device 10. The device 10 is actuated in a state approximate to the actual working conditions. In such a way, the appropriate evaluation is secured.

5. 发明专利

JPS59229633A LOGICAL CIRCUIT DEVICE 失效
公开(公告)号：JPS59229633A
公开(公告)日：1984-12-24
申请号：JP10257683
申请日：1983-06-10
申请人： HITACHI LTD
发明人： HOTSUTA SHINKICHI , IWATA KATSUMI , FUNATSU KENZOU
IPC分类号： G06F1/24 , G06F1/00
摘要： PURPOSE:To preset prescribed data simply for a short time by providing the titled device with the 1st circuit means for simultaneously driving respective word lines and the 2nd circuit means for simultaneously applying the logical state of ''1'' or ''0''. CONSTITUTION:Many memory cells M are arrayed like a matrix. To select and drive an optional memory cell out of the many memory cells M, word lines W and data lines Da, Db are connected. The word lines W and the data lines Da, Db are alternatively selected and driven by decoder outputs Y0-Y4 and X0-X2 from an address decoder. Respective data lines Da, Db are connected to common data lines DA, DB in common through MOSFETs Qa, Qb respectively. The MOSFETs Qa, Qb are driven by the column selecting decoder outputs X0-X2.

6. 发明专利

JPS59208944A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路设备
公开(公告)号：JPS59208944A
公开(公告)日：1984-11-27
申请号：JP8262583
申请日：1983-05-13
申请人： Hitachi Ltd
发明人： FUNATSU KENZOU , IWATA KATSUMI , HOTSUTA SHINKICHI
IPC分类号： H03K19/177
CPC分类号： H03K19/1772
摘要： PURPOSE:To attain a high speed and small power consumption with a simple circuit constitution for a semiconductor IC device by dividing the array of output lines of an AND array with specific non-inverse and inverse signals to use this divided output line to an input line and therefore dividing also an OR array in the same way to deliver the corresponding output line with a wired logic constitution. CONSTITUTION:Input signals x0 and -x0, for example, are used among complementary input signals consisting of specific non-inverse and inverse signals, and the array of output lines are divided into left and right. For instance, the non-reverse input signal x0 is set at a high level and therefore one of the output line groups of the right side is selected. While one of the output line groups of the left side is selected when the inverse input signal x0 is set at a high level. The enhancement type MOSFETQ5, etc. shown by circle marks are set between the output lines of an OR array and precharge MOSFETQ3, etc. shown also by circle marks. Then the signal -x0 is impressed to the MOSFET of the right side; while the signal x0 is impressed to the MOSFET of the left side. In such a way, an output line of the right side is selected with the signal x0 set at a high level, and at the same time the MOSFET of the OR array (L) of the left side is turned off. Thus a useless precharging action is inhibited.
摘要翻译：目的：为了通过将AND阵列的输出线的阵列用特定的非反相和反相信号进行划分，通过简单的半导体IC器件的电路结构来实现高速度和低功耗，以将该分割的输出线用于输入线并且因此也以相同的方式划分OR阵列以传送具有有线逻辑结构的相应输出线。构成：例如，在由特定非反相和反相信号组成的互补输入信号中使用输入信号x0和-x0，输出线阵列分为左右。例如，非反向输入信号x0被设定为高电平，因此选择右侧的输出线组之一。当反相输入信号x0设置在高电平时，选择左侧的输出线组之一。在OR阵列的输出线和预充电MOSFETQ3之间设置由圆形标记表示的增强型MOSFETQ5等，也由圆圈标记表示。然后将信号-x0施加到右侧的MOSFET; 而信号x0被施加到左侧的MOSFET。以这种方式，以设定为高电平的信号x0选择右侧的输出线，同时关闭左侧的OR阵列（L）的MOSFET。因此，无用的预充电动作被抑制。

7. 发明专利

JPS59206968A Eprom mounted type microcomputer 失效
标题翻译： EPROM安装型微型计算机
公开(公告)号：JPS59206968A
公开(公告)日：1984-11-22
申请号：JP8086283
申请日：1983-05-11
申请人： Hitachi Ltd
发明人： IWATA KATSUMI , FUNATSU KENZOU , HOTSUTA SHINKICHI
IPC分类号： G06F12/04 , G06F9/32 , G06F11/36 , G06F12/06 , G06F15/78
CPC分类号： G06F15/78 , G06F11/36
摘要： PURPOSE:To facilitate development and correction of programs by making an EPROM accessed at least twice during one cycle of operation clock of a microprocessor. CONSTITUTION:A mask ROM1 that stores a program and an RAM2 that stores data are accessed separately by a CPU3. The CPU3 has an instruction register IR, a program counter PC, an arithmetic logic unit ALU, an accumulator ACC, registers IX, DR and a controlling section 3a. Externally attached EPROM10 is accessed at least twice during one cycle of operation clock of the CPU3, and instruction codes stored in even number addresses and odd number addresses are read out. The instruction codes are latched by a latch circuit 6 and then taken in an instruction register IR in the CPU3.
摘要翻译：目的：通过在微处理器的一个周期的一个周期内使EPROM访问至少两次来促进程序的开发和修正。构成：存储程序的掩码ROM1和存储数据的RAM2由CPU3单独访问。 CPU3具有指令寄存器IR，程序计数器PC，算术逻辑单元ALU，累加器ACC，寄存器IX，DR和控制部分3a。外部连接的EPROM10在CPU3的一个周期的操作时钟期间被访问至少两次，并且读出存储在偶数地址和奇数地址中的指令代码。指令代码由锁存电路6锁存，然后取入CPU3中的指令寄存器IR。

8. 发明专利

JPS59191652A Microcomputer 失效
标题翻译：微机
公开(公告)号：JPS59191652A
公开(公告)日：1984-10-30
申请号：JP6546283
申请日：1983-04-15
申请人： Hitachi Ltd
发明人： IWATA KATSUMI , FUNATSU KENZOU , HOTSUTA SHINKICHI
IPC分类号： G06F11/22 , G06F9/30 , G06F9/32 , G06F15/78
摘要： PURPOSE: To attain freely a function test, etc. of an input and output terminals by supplying a test program, for example, from outside to execute it through a CPU even if no program input terminal is available.
CONSTITUTION: The output data Do latched by a buffer I1 is activated by a data output clock ϕo within the first half cycle of a CPU12 and appears at a data output terminal Po. This terminal Po is cut off from the buffer I1 and ready to accept the input of the external data in the second cycle of the CPU12. Under such conditions, a program Dp supplied to the terminal Po is applied to a latch circuit 20a. The program Dp given from outside can be fed and executed by the CPU12 by an input clock ϕp within the second half cycle of the CPu12. In other words, the terminal Po can be shared as an input terminal of the program Dp.
COPYRIGHT: (C)1984,JPO&Japio
摘要翻译：目的：通过从外部提供测试程序，即使没有程序输入端子可用，也可以通过CPU自由地执行输入和输出端子的功能测试等来执行。构成：由缓冲器I1锁存的输出数据由CPU12的前半周期内的数据输出时钟phi激活，出现在数据输出端Po。该端子Po从缓冲器I1切断并准备好接受CPU12的第二个周期中的外部数据的输入。在这种条件下，提供给端子Po的程序Dp被施加到锁存电路20a。由CPU12通过CPu12的后半周期内的输入时钟phip馈送并执行从外部给出的程序Dp。换句话说，终端Po可以被共享为节目Dp的输入终端。

9. 发明专利

JPS60245049A DATA PROCESSOR 失效
公开(公告)号：JPS60245049A
公开(公告)日：1985-12-04
申请号：JP10047984
申请日：1984-05-21
申请人： HITACHI LTD
发明人： FUNATSU KENZOU
IPC分类号： G06F9/46 , G06F9/40 , G06F9/42 , G06F9/48
摘要： PURPOSE:To shorten an interruption reaction time without increasing the capacity of a ROM by setting a flag corresponding to a register to be saved by a user through a program, and minimising the number of cycles reqiured to reload the register. CONSTITUTION:The contents of a tag register TR are supplied from an instruction decoder ID to a sequence controller SC through gates g1-gn. A controller SC when an interruption is initiated outputs the contents of only registers corresponding to tab bits set to 1 to a bus BUS except registers corresponding to tag bits set to 0 according to priority predetermined on the basis of the contents of the register TR. Simultaneously, the contents of a stack pointer SP are decreased and data from the BUS are stored in address locations of the stack area in the RAM that the pointer SP indicates. The controller SC when receiving a return interrupt instruction reloads the contents of the stand-by registers in the RAM to the original registers successively.

10. 发明专利

JPS60218137A MICROCOMPUTER SYSTEM 失效
公开(公告)号：JPS60218137A
公开(公告)日：1985-10-31
申请号：JP7280984
申请日：1984-04-13
申请人： HITACHI LTD
发明人： FUNATSU KENZOU
IPC分类号： G06F9/30 , G06F9/34
摘要： PURPOSE:To reduce the capacity of a ROM through simple change in hardware by accessing a RAM on the basis of an one-word instruction to which an operand indicating the high-order or low-order bit of an address in a prescribed memory is added together with an operation code. CONSTITUTION:An instruction constituting one word of 10 bits is supplied from the ROM to an instruction decoder ID to output various control signal and pass the low-order four bits e.g. of an instruction code. On the other hand, X and Y registers XR, YR or the like constituted of four bits respectively access the RAM through X and Y address decoder (DEC) or the like and gate circuits G1, G2 connected between the YR and the Y-DEC are controlled by a control signal from the ID. An instruction constituted of an operation code consisting of high-order six bits and an operant consisting of low-order four bits is formed, and when the instruction is read out from the ROM, the circuit G2 is opened, the low-order four bits are inputted to the Y-DEC and the RAM can be continuously read out.

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