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1. 发明专利

JP2001125786A DEVICE AND SYSTEM FOR PROCESSING DATA 失效
公开(公告)号：JP2001125786A
公开(公告)日：2001-05-11
申请号：JP30632899
申请日：1999-10-28
申请人： HITACHI LTD , HITACHI HOKKAI SEMICONDUCTOR
发明人： TOMONAGA KAZUHIRO , IWATA KATSUMI
IPC分类号： G06F9/32 , G06F9/34 , G06F12/02 , G06F12/06 , G06F13/16 , G06F15/78
摘要： PROBLEM TO BE SOLVED: To relax the limitation of program capacity while maintaining satisfactory program execution efficiency in the comparatively small access space of a CPU in a data processor. SOLUTION: A data processor 1 has a normal mode with the narrow access space of a CPU 2 and an advanced mode with the wide access space. Even in the normal mode, a transfer control part 3 enables data transfer control over an address range accessible for the CPU at that time. Even when a program or the like is generated over the limitation of program capacity in respect to the access range of the CPU in the normal mode, by storing the program just for the excess of that limitation in the non-access area of a ROM 6 in the normal mode, the transfer control part can access this program and can transfer it to a RAM 7 and the CPU in the normal mode can access and utilize the program or the like transferred to the RAM.

2. 发明专利

JPH0444426B2 失效
公开(公告)号：JPH0444426B2
公开(公告)日：1992-07-21
申请号：JP722283
申请日：1983-01-21
申请人： HITACHI LTD
发明人： IWATA KATSUMI , KUBOKI SHIGEO , BABA SHIRO
IPC分类号： H03M1/76 , H01L21/822 , H01L27/04 , H01L27/08

3. 发明专利

JPS6489000A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPS6489000A
公开(公告)日：1989-04-03
申请号：JP24377087
申请日：1987-09-30
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： TANABE HIROKI , ISHIBASHI KENICHI , IWATA KATSUMI , ITO TAKASHI
IPC分类号： G11C17/00 , G11C29/00 , G11C29/02
摘要： PURPOSE:To shorten a testing time while using a PROM writer on the market by supplying a specified logical value to a specified terminal from the outside and allowing the switching of the two modes of read/write at every word and read/write for plural words to be possible in a semiconductor IC incorporating a PROM. CONSTITUTION:When the logical value zero is inputted to the PROM test mode terminal 1, the address of the PROM part is decided by the OR of an address most significant bit terminal 5 and a chip enable terminal 8. Therefore, when the terminal 8 takes the logical value 1, one of a low-order, and a high-order data input/output terminal 6 and 7 is made to be an active input/output port. When the logical value from the terminal is 1, a low-order and a high-order mat 2 and 3 are made to be an enable state and the terminals 6 and 7 go to active regardless of the value of the terminal 5 when a chip is selected by the terminal 8. Thus, the testing time is about 1/2 in comparison with the case that this mode is not used.

4. 发明专利

JPS6220415A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS6220415A
公开(公告)日：1987-01-29
申请号：JP15813085
申请日：1985-07-19
申请人： HITACHI LTD
发明人： IWATA KATSUMI , TSUJI MITSUO , KOJIMA HARUO
IPC分类号： H03K17/687 , G09G3/12 , G09G3/20
摘要： PURPOSE:To extent the dynamic range of an output MOSTFET by connecting a depletion type MOSFET, which clamps a high voltage for display, to the drain terminal of a driving MOSFET. CONSTITUTION:When a signal D to be outputted is in the low level, a driving MOSFET Q1 is turned on, and the drain output outputted from the FET Q1 goes to the same high level as a power source Vcc, and an output MOSFET Q3 is turned off. When the signal D to be outputted is in the high level, the FET Q1 is turned off. Since a depletion type MOSFET Q2 connected to a high voltage -Vdisp for display having a polarity opposite to that of the supply voltage Vcc is connected to the drain of the FET Q1, the drain terminal has a negative threshold voltage of the FET Q2. As the result, a large-amplitude display output signal is generated in the output of the output FET Q3.

5. 发明专利

JPH07302241A DATA PROCESSOR 失效
公开(公告)号：JPH07302241A
公开(公告)日：1995-11-14
申请号：JP11452694
申请日：1994-04-28
申请人： HITACHI LTD , HITACHI HOKKAI SEMICONDUCTOR
发明人： HORIUCHI MICHIHIRO , IWATA KATSUMI
IPC分类号： G06F15/167 , G06F13/38 , G06F15/163
摘要： PURPOSE:To provide a technique for enlarging the capacity of a multi-port buffer memory to be formed in a data processor on-chip while avoiding increase of a chip size. CONSTITUTION:This data processor 1 provided with a RAM 20 accessable by a central processing unit 10, bi-directional data buffer means 60 and 65 to be the buffers of the RAM capable of transferring data from both internal and external directions and a DMAC 70 for controlling data transfer between the RAM and the bi-directional data buffer means is capable of diverting the RAM to the storage area of transfer data and enlarges the capacity of the practical buffer memory while avoiding the increase of the chip size.

6. 发明专利

JPH01314292A DYNAMIC DISPLAY SYSTEM 失效
公开(公告)号：JPH01314292A
公开(公告)日：1989-12-19
申请号：JP14571888
申请日：1988-06-15
申请人： HITACHI LTD
发明人： HORIUCHI KENJI , IWATA KATSUMI
IPC分类号： G09G3/12
摘要： PURPOSE:To perform a stable display even if the number of display digits is changed by changing the pulse width of a digit signal corresponding to the number of display digits or inserting a display blanking period in a frame period after making the pulse width of the digit signal constant and keeping the frequency of frame constant regardless of the number of display digits. CONSTITUTION:By changing the pulse width of the digit signal corresponding to the number of display digits, the frequency of the frame can be made constant regardless of the number of display digits. Even if the number of display digits is changed, the fluctuation, flicker or beat, etc., of the display can be prevented from occurring and the stable display action can be performed. By making the pulse width of the digit signal constant and inserting the display blanking period in the frame period if necessary, the frame period can be made constant regardless of the number of display digits. Even if the number of display digits is changed, the fluctuation, flicker or the beat, etc., of the display can be prevented from occurring and the stable display action can be performed.

7. 发明专利

JPS63208091A CHARACTER GENERATOR 失效
公开(公告)号：JPS63208091A
公开(公告)日：1988-08-29
申请号：JP4025687
申请日：1987-02-25
申请人： HITACHI LTD
发明人： HORIUCHI KENJI , IWATA KATSUMI
IPC分类号： G06F3/153 , G09G1/14 , G09G5/24

8. 发明专利

JPS59229633A LOGICAL CIRCUIT DEVICE 失效
公开(公告)号：JPS59229633A
公开(公告)日：1984-12-24
申请号：JP10257683
申请日：1983-06-10
申请人： HITACHI LTD
发明人： HOTSUTA SHINKICHI , IWATA KATSUMI , FUNATSU KENZOU
IPC分类号： G06F1/24 , G06F1/00
摘要： PURPOSE:To preset prescribed data simply for a short time by providing the titled device with the 1st circuit means for simultaneously driving respective word lines and the 2nd circuit means for simultaneously applying the logical state of ''1'' or ''0''. CONSTITUTION:Many memory cells M are arrayed like a matrix. To select and drive an optional memory cell out of the many memory cells M, word lines W and data lines Da, Db are connected. The word lines W and the data lines Da, Db are alternatively selected and driven by decoder outputs Y0-Y4 and X0-X2 from an address decoder. Respective data lines Da, Db are connected to common data lines DA, DB in common through MOSFETs Qa, Qb respectively. The MOSFETs Qa, Qb are driven by the column selecting decoder outputs X0-X2.

9. 发明专利

JPS59208944A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路设备
公开(公告)号：JPS59208944A
公开(公告)日：1984-11-27
申请号：JP8262583
申请日：1983-05-13
申请人： Hitachi Ltd
发明人： FUNATSU KENZOU , IWATA KATSUMI , HOTSUTA SHINKICHI
IPC分类号： H03K19/177
CPC分类号： H03K19/1772
摘要： PURPOSE:To attain a high speed and small power consumption with a simple circuit constitution for a semiconductor IC device by dividing the array of output lines of an AND array with specific non-inverse and inverse signals to use this divided output line to an input line and therefore dividing also an OR array in the same way to deliver the corresponding output line with a wired logic constitution. CONSTITUTION:Input signals x0 and -x0, for example, are used among complementary input signals consisting of specific non-inverse and inverse signals, and the array of output lines are divided into left and right. For instance, the non-reverse input signal x0 is set at a high level and therefore one of the output line groups of the right side is selected. While one of the output line groups of the left side is selected when the inverse input signal x0 is set at a high level. The enhancement type MOSFETQ5, etc. shown by circle marks are set between the output lines of an OR array and precharge MOSFETQ3, etc. shown also by circle marks. Then the signal -x0 is impressed to the MOSFET of the right side; while the signal x0 is impressed to the MOSFET of the left side. In such a way, an output line of the right side is selected with the signal x0 set at a high level, and at the same time the MOSFET of the OR array (L) of the left side is turned off. Thus a useless precharging action is inhibited.
摘要翻译：目的：为了通过将AND阵列的输出线的阵列用特定的非反相和反相信号进行划分，通过简单的半导体IC器件的电路结构来实现高速度和低功耗，以将该分割的输出线用于输入线并且因此也以相同的方式划分OR阵列以传送具有有线逻辑结构的相应输出线。构成：例如，在由特定非反相和反相信号组成的互补输入信号中使用输入信号x0和-x0，输出线阵列分为左右。例如，非反向输入信号x0被设定为高电平，因此选择右侧的输出线组之一。当反相输入信号x0设置在高电平时，选择左侧的输出线组之一。在OR阵列的输出线和预充电MOSFETQ3之间设置由圆形标记表示的增强型MOSFETQ5等，也由圆圈标记表示。然后将信号-x0施加到右侧的MOSFET; 而信号x0被施加到左侧的MOSFET。以这种方式，以设定为高电平的信号x0选择右侧的输出线，同时关闭左侧的OR阵列（L）的MOSFET。因此，无用的预充电动作被抑制。

10. 发明专利

JP2002342256A DATA PROCESSOR AND METHOD FOR UPDATING DATA TABLE 失效
公开(公告)号：JP2002342256A
公开(公告)日：2002-11-29
申请号：JP2001142499
申请日：2001-05-14
申请人： HITACHI LTD , HITACHI HOKKAI SEMICONDUCTOR , KOKUSAI ELECTRIC ALHPA CO LTD
发明人： KOYAMA HIDEMI , IWATA KATSUMI , IIDA YOSHIKAZU , FUKAZAWA SHINICHI , FUJIMOTO TSUKASA
IPC分类号： G06F13/12 , G06F3/00 , G06F9/445 , G06F13/00 , G06F13/38 , G06K17/00
摘要： PROBLEM TO BE SOLVED: To provide a data processor, capable of readily facilitating countermeasures to the addition and change of interface specifications represented by the command specifications of the target equipment of interface control. SOLUTION: In an interface controller (3), first control information to be applied to a first latch means (CMDR) for controlling the operation of target equipment (6) of interface control, connected to the interface controller (3) and second control information to be applied to second latch means (MDR, CTR, RTR) for controlling the interface operation with the target equipment of interface control are made correspond to each other, so as to be respectively defined. When a command specified for the target equipment of the interface control is added or changed, countermeasures are facilitated, by independently correcting the both control information concerning the transmission of the command to the target equipment of interface control and the interface control operation of the interface controller itself.

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