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    • 3. 发明专利
    • Semiconductor memory
    • 半导体存储器
    • JP2003068071A
    • 2003-03-07
    • JP2001261132
    • 2001-08-30
    • Hitachi LtdHitachi Ulsi Systems Co Ltd株式会社日立製作所株式会社日立超エル・エス・アイ・システムズ
    • INOUE YOSHIHIKOKIMURA HISASHIHORIGUCHI SHINJI
    • G11C11/401G11C11/403G11C11/406G11C29/00G11C29/04
    • G11C11/406
    • PROBLEM TO BE SOLVED: To provide a semiconductor memory in which a refresh-cycle time can be shortened.
      SOLUTION: This semiconductor memory has regular memory cells provided at the prescribed intersections of a plurality of regular word lines and a plurality of bit lines and redundant memory cells provided at the prescribed intersections of redundant word lines and the plurality of bit lines, it is discriminated whether each of internal address signals and refresh-address signals for memory operation corresponds to an address of a defective word line out of the plurality of regular word lines or not by a redundant relieving circuit, and a defective word line caused in a regular word line is switched to a redundant word line by an address selecting circuit in accordance with the discriminated result. In the redundant relieving circuit, it is discriminated whether a refresh- address in which 1 is added to the refresh-address signal corresponds to a defective address or not, in the address selecting circuit, selecting operation of a regular word line or a redundant word line is performed conforming to the discriminated result in a previous cycle during refresh-operation.
      COPYRIGHT: (C)2003,JPO
    • 要解决的问题:提供可以缩短刷新周期时间的半导体存储器。 解决方案:该半导体存储器具有设置在冗余字线和多个位线的规定交点处的多个常规字线和多个位线和冗余存储单元的规定交点处的规则存储单元, 用于存储器操作的内部地址信号和刷新地址信号中的每一个是否对应于多个常规字线中的缺陷字线的地址,而不是由冗余解除电路,以及在正常字线中引起的有缺陷的字线 根据鉴别结果由地址选择电路切换到冗余字线。 在冗余消除电路中,区分在地址选择电路中,在刷新地址信号中添加1的刷新地址是否对应于缺陷地址,选择正常字线或冗余字的操作 在刷新操作期间,在前一周期中符合判别结果执行线。