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1. 发明专利

JPH0550017B2 失效
公开(公告)号：JPH0550017B2
公开(公告)日：1993-07-27
申请号：JP24548983
申请日：1983-12-28
申请人： HITACHI LTD
发明人： SUMIMOTO TSUTOMU , KATO MASAO
IPC分类号： G06F12/08 , G06F12/04
摘要： PURPOSE:To solve easily and surely a problem of destruction of a new data in a share memory due to a special full write by suppressing the special full write when a write address belongs to a block copied to a buffer memory so as to process it as a partial write. CONSTITUTION:A processing unit (CPU) 1 has a buffer memory 2 and its address registration directory (BAA) 3 and the access request to a main memory is processed all by an access request control section (RQCTL) 4. Another processing unit (IOP) 100 is provided with an access request control section 11. When a write request from the IOP100 enters an access request buffer N (RQBFB) 21, a write request is received by a reception control circuit (PRI) 30 and the write to a main memory (MS) 50 is conducted in the said address. An address registration directory (FAA) 40 being a copy of the BAA3 as to the address is referenced and when its address exists in the FAA40, the block registration is made ineffective and the registration of the said block in the BA3 is cancelled.

2. 发明专利

JPH0465547B2 失效
公开(公告)号：JPH0465547B2
公开(公告)日：1992-10-20
申请号：JP3327983
申请日：1983-03-01
申请人： HITACHI LTD
发明人： MINAMI HIDEKAZU , ARAI KYOKAZU , SUMIMOTO TSUTOMU , IKEDA KOICHI
IPC分类号： H01L21/822 , G06F5/06 , H01L21/60 , H01L21/82 , H01L27/04 , H01L27/118

3. 发明专利

JPH0157820B2 失效
公开(公告)号：JPH0157820B2
公开(公告)日：1989-12-07
申请号：JP6765484
申请日：1984-04-06
申请人： HITACHI LTD
发明人： KUMAGAI TAKASHI , SUMIMOTO TSUTOMU , TANIGUCHI TOSHIHISA
IPC分类号： G06F12/08
摘要： PURPOSE:To improve the through-out of a memory access of an input/output processing unit by checking an address in a block of access request to select whether the data is transferred in a form of block transfer or transferred directly from a main storage device to the input/output processing unit. CONSTITUTION:Suppose that a desired data does not exists in a buffer storage device (BS) 5 through the access from the input/output processing unit (IOP)2. When the 5th, 6th bits of an address register 3 are ''11'', a control circuit 6 starts a main storage device (MS) 7 so that a desired 16-byte data 34 only is transferred to the IOP2 through a data line 14. Regardless of above processing, the data is reduced to useless, since the 16-byte data 31-33 in the block are not fetched by this channel after the 16-byte data 34 is fetched even if a block 30 of the MS7 is transferred to the BS5. Thus, the direct transfer of the desired 16-byte data 34 only from the MS7 to the IOP2 has far less time.

4. 发明专利

JPH01270296A ELECTRONIC APPARATUS AND ITS COOLING METHOD 失效
公开(公告)号：JPH01270296A
公开(公告)日：1989-10-27
申请号：JP9813488
申请日：1988-04-22
申请人： HITACHI LTD , HITACHI COMPUTER ENG
发明人： KUMAGAI TAKASHI , OGURO TAKAHIRO , KATO MASAO , SUMIMOTO TSUTOMU , FURUNO SADAAKI
IPC分类号： H05K7/20 , H01L23/46 , H01L23/467
摘要： PURPOSE:To enable the cooling of semiconductor elements of large heating value, and realize the reduction of noise and the miniaturization of a cooling equipment, by air-cooling the semiconductor elements after the feeding air for the semiconductor elements is previously cooled. CONSTITUTION:As a cooling medium for an electronic apparatus provided with a plurality of semiconductor elements, air is used, which is previously cooled prior to the feeding of air to a semiconductor element circuit. As a result, high cooling capability is attained even by forced air-cooling, and semiconductor elements of large heating value can be effectively cooled. In the case where a refrigeration equipment is used as a cooling means of feeding air, a refrigeration cycle is repeated by a condenser 11, a compressor 14, an expansion valve 12 and an evaporator 13. The air fed to the electronic apparatus is cooled by the evaporator 13, and the semiconductor elements are cooled by said cooled air. Thereby, in the case of an electronic apparatus whose heating value is comparatively large, necessary cooling effect is attained, and the reduction of noise and the miniaturization of a cooling equipment can be realized.

5. 发明专利

JPH01215098A COOLING SYSTEM 失效
公开(公告)号：JPH01215098A
公开(公告)日：1989-08-29
申请号：JP4129388
申请日：1988-02-24
申请人： HITACHI LTD
发明人： KUMAGAI TAKASHI , KATO MASAO , SUMIMOTO TSUTOMU , YAMAZAKI SUSUMU , YANAGIDA TAKEHIKO
IPC分类号： H05K7/20 , H01L23/36 , H01L23/46 , H01L23/467
摘要： PURPOSE:To enable temperature rise in a heating unit of a following stage to be controlled within a specified value without the amount of air blasting being increased and a large fin being employed, by a structure wherein both a low fin density section and a high fin density section are provided in a set of fins which are installed to each the heating unit in the cooling passage, and the heating units adjacent to each other are disposed to be reversed with respect to the fin density. CONSTITUTION:With a preceding heat sink 11, the fin density of the upper half section 24 is high (i.e., dense) while the fin density of the lower half section 25 is low (i.e., non-dense). On the contrary, with a following heat sink 12, the fin density of the upper half section 29 is low (non-dense) while the fin density of the lower section 30 is high (dense). That is, the preceding heat sink 11 and the following heat sink 12 are disposed so that with the respective set of fins, the high fin density sections or the low fin density sections are not opposite to each other. When a cooling fluid is caused to flow in the direction indicated by an arrow, with the preceding heat sink 11, the high fin density section 24 has a large heat transfer area. Therefore, the high fin density section 24 thermally exchanges a large heating value with the cooling fluid, compared with that of the low fin density section 25, which results in increasing of temperature in the cooling fluid.

6. 发明专利

JPS6236318B2 失效
公开(公告)号：JPS6236318B2
公开(公告)日：1987-08-06
申请号：JP22684482
申请日：1982-12-27
申请人： HITACHI LTD
发明人： SUMIMOTO TSUTOMU , ISHAMA AKIRA , KAMIJO YOSHIO
IPC分类号： G11C29/00 , G01R31/28 , G11C29/02 , G11C29/08 , G11C29/56

7. 发明专利

JPS61229142A ARRAY MANAGING DEVICE FOR CONTROLLING REPLACEMENT IN BUFFER MEMORY SYSTEM HAVING HIERARCHICAL CONSTITUTION 失效
公开(公告)号：JPS61229142A
公开(公告)日：1986-10-13
申请号：JP7002785
申请日：1985-04-04
申请人： HITACHI LTD
发明人： SUMIMOTO TSUTOMU
IPC分类号： G06F12/08 , G06F12/12
摘要： PURPOSE:To prevent inappropriate replacement in a buffer memory system having hierarchical constitution, by updating the content of a host array for controlling replacement even if access to a host buffer memory is not necessary. CONSTITUTION:A registering address array provided in a subordinate buffer memory 2 is retrieved in relation with an address 21 from an ADR 20. When the address is registered, a bit signal 22 is generated and a tag having a specific bit pattern representing a replacement controlling array (WRA) updating request is generated by driving a tag generator 27, and then, the tag is sent out through a signal line 11. The WRA updating request accepted by a acceptance controlling circuit 7 is checked by a tag decoder 31 and, when the designated address is found as a result of the retrieval by means of the registering address array 8, a bit signal 35 actuates a WRA updating circuit 34 and causes a WRA 9 to be updated in accordance with an ordinary LRU system.

8. 发明专利

JPS58178454A Memory controlling system 失效
标题翻译：内存控制系统
公开(公告)号：JPS58178454A
公开(公告)日：1983-10-19
申请号：JP6105282
申请日：1982-04-14
申请人： Hitachi Ltd , Nippon Telegr & Teleph Corp
发明人： SUMIMOTO TSUTOMU , ABE SHIYUUICHI
IPC分类号： G06F13/42 , G06F12/00 , G06F13/18 , G06F15/16 , G06F15/177
CPC分类号： G06F13/18
摘要： PURPOSE:To speed up memory access from a CPU, by providing two groups of processor systems with buses individually, providing accepting circuits respectively, and performing two-phase-level acceptance while making operation phases different. CONSTITUTION:An access request from a CPU5 is sent to a memory 100 through a signal line 35 and inputted to an accepting circuit 41. When it is accepted, the output signal of an FF6 is sent out to the CPU5, which sends a memory address and control information through a bus 11 by the received signal. In response to a write request from the CPU5, the CPU5 accepting a signal sends a write address, write data, and control information to the memory 100 through the bus 11. When CPUs 5-6 generate memory access requests at the same time, the accepting circuit 41 receives the requests invariably with priority given to the CPU5. The circuit 41 accepts the request after precedent memory access is completed in a busy state.
摘要翻译：目的：为了加速CPU的存储器访问，通过分别提供两组处理器系统的总线，分别提供接收电路，并且在使操作阶段不同的情况下进行两阶段接收。构成：来自CPU5的访问请求通过信号线35发送到存储器100并输入到接受电路41.当接受FF6的输出信号被发送到CPU5，CPU5发送存储器地址并通过接收到的信号通过总线11控制信息。响应于来自CPU5的写入请求，接收信号的CPU5通过总线11向存储器100发送写入地址，写入数据和控制信息。当CPU5-6同时生成存储器访问请求时，接收电路41不可避免地接收到对CPU5优先给予的请求。电路41在繁忙状态下完成先前存储器访问之后接受该请求。

9. 发明专利

JPS5868156A INTEGRATED CIRCUIT 失效
公开(公告)号：JPS5868156A
公开(公告)日：1983-04-22
申请号：JP16634681
申请日：1981-10-20
申请人： HITACHI LTD
发明人： ISHIYAMA AKIRA , KAMIJIYOU YOSHIO , SUMIMOTO TSUTOMU
IPC分类号： G06F7/00 , G01R31/316 , G06F11/22
摘要： PURPOSE:To test an integrated circuit efficiently by individually providing input terminals for supplying a reset signal to the 1st group of flip-flop in common, and another input terminals for supplying a reset signal to the 2nd group of flip- flops in common. CONSTITUTION:A reset signal 11 for an FF group 9 is fixed to ''0''. Then, a diagnostic control circuit sets diagnostic data to the input FF group 9 and input pin 6 of a combinational circuit 3 to be diagnosed. After the output of this combinational circuit 3 is settled, a set clock 8 is applied to an output FF10, and the output of the combinational circuit 3 is latched in the FF10. Pieces of information in the output FF10 and of an outut pin 7 are read out to the diagnostic control circuit and compared with an expected value to diagnose a fault. Once ''1'' is set to the FF10 for the confirmation of the normalcy of some gate in the circuit 3, a signal from the reset terminal 12 of the FF group 10 is set to ''1'' in a successive cycle, thereby initializing the output FF10.

10. 发明专利

JPS5538674A LOGOUT SYSTEM OF MEMORY CONTROLLER 失效
公开(公告)号：JPS5538674A
公开(公告)日：1980-03-18
申请号：JP11170778
申请日：1978-09-13
申请人： HITACHI LTD
发明人： OKABE TOSHIHIRO , SUMIMOTO TSUTOMU
IPC分类号： G06F12/16 , G06F3/06 , G06F11/34 , G11C29/00
摘要： PURPOSE:To enable a memory controller in a system operation state to collect data when a temporarily fault occurs by controlling the freeze release of the access acception of the memory controller, the logout of the internal state at fault time and storage to an external memory through a fault processor. CONSTITUTION:When fault generating circuit 21 of memory controller 1 detects a fault such as address and parity errors, FF22 is set to close AND gates 16 and 17 through OR circuit 20, thereby freezing the access acception of address acception circuit 18 while the set output of fault detection FF22 is supplied to the fault processor. Consequently, the fault processor reads out the states of acception detection FF19 of circuit 1 and a register and stores them in an external memory. Then, the fault processor resets FF22 to release the acception freeze of access of circuit 1. Those operations are carried out automatically and when a temporarily fault occurs, status data at the time of the fault of the memory controller can be collected while the operation of a system including CPU is carried on.

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