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1. 发明专利

JPS5779556A Microprogram control system 失效
标题翻译：微控制系统
公开(公告)号：JPS5779556A
公开(公告)日：1982-05-18
申请号：JP15353680
申请日：1980-10-31
申请人： Hitachi Ltd , Nippon Telegr & Teleph Corp
发明人： NAKAMURA TOSHIO , ABE SHIYUUICHI
IPC分类号： G06F9/22 , G06F9/26 , G06F9/42
CPC分类号： G06F9/262
摘要： PURPOSE:To decrease the number of microinstruction by executing a following microinstruction according to whether the control is returned to a branch origin or not, by providing a state holding circuit which informs that a branch to a subroutine is done when a microinstruction for the branch is executed. CONSTITUTION:When a microinstruction in an address indicated by an address register 2 is read to a data register 3 to specify a microorder CALL, a decoder 4 decodes the contents into a return address from a subroutine to hold it in a return address register 5, and a following branch address is set from a control storage address field CMAF to the register 2; and further, a branch state holding circuit (flip-flop) 6 is set by the microinstruction order CALL to perform branching operation. Once a microinstruction order RTN is specified, a control circuit 7 discriminates the state of the circuit 6; when it is in an on-state, the return address is transferred to the register 2 for returning the control to the branch origin, and when in an off-state control over the execution of the following microinstruction is exercised.
摘要翻译：目的：通过提供一种状态保持电路来通过执行以下微指令来减少微指令的数量，该状态保持电路当分支的微指令为执行。构成：当由地址寄存器2指示的地址中的微指令被读取到数据寄存器3以指定微顺序CALL时，解码器4将内容从子程序解码为返回地址以将其保存在返回地址寄存器5中，并且从控制存储地址字段CMAF向寄存器2设置以下分支地址; 此外，通过微指令命令CALL设置分支状态保持电路（触发器）6以进行分支操作。一旦指定了微指令命令RTN，则控制电路7区分电路6的状态; 当它处于开状态时，返回地址被传送到寄存器2，用于将控制返回到分支来源，并且当处于关闭状态时执行下一个微指令的控制。

2. 发明专利

JPS58178454A Memory controlling system 失效
标题翻译：内存控制系统
公开(公告)号：JPS58178454A
公开(公告)日：1983-10-19
申请号：JP6105282
申请日：1982-04-14
申请人： Hitachi Ltd , Nippon Telegr & Teleph Corp
发明人： SUMIMOTO TSUTOMU , ABE SHIYUUICHI
IPC分类号： G06F13/42 , G06F12/00 , G06F13/18 , G06F15/16 , G06F15/177
CPC分类号： G06F13/18
摘要： PURPOSE:To speed up memory access from a CPU, by providing two groups of processor systems with buses individually, providing accepting circuits respectively, and performing two-phase-level acceptance while making operation phases different. CONSTITUTION:An access request from a CPU5 is sent to a memory 100 through a signal line 35 and inputted to an accepting circuit 41. When it is accepted, the output signal of an FF6 is sent out to the CPU5, which sends a memory address and control information through a bus 11 by the received signal. In response to a write request from the CPU5, the CPU5 accepting a signal sends a write address, write data, and control information to the memory 100 through the bus 11. When CPUs 5-6 generate memory access requests at the same time, the accepting circuit 41 receives the requests invariably with priority given to the CPU5. The circuit 41 accepts the request after precedent memory access is completed in a busy state.
摘要翻译：目的：为了加速CPU的存储器访问，通过分别提供两组处理器系统的总线，分别提供接收电路，并且在使操作阶段不同的情况下进行两阶段接收。构成：来自CPU5的访问请求通过信号线35发送到存储器100并输入到接受电路41.当接受FF6的输出信号被发送到CPU5，CPU5发送存储器地址并通过接收到的信号通过总线11控制信息。响应于来自CPU5的写入请求，接收信号的CPU5通过总线11向存储器100发送写入地址，写入数据和控制信息。当CPU5-6同时生成存储器访问请求时，接收电路41不可避免地接收到对CPU5优先给予的请求。电路41在繁忙状态下完成先前存储器访问之后接受该请求。

3. 发明专利

JPS59158442A Instruction read control system 失效
标题翻译：指令读取控制系统
公开(公告)号：JPS59158442A
公开(公告)日：1984-09-07
申请号：JP3327883
申请日：1983-03-01
申请人： Hitachi Ltd
发明人： YAMAMOTO MICHITAKA , ABE SHIYUUICHI , WADA KENICHI
IPC分类号： G06F9/38 , G06F9/32
摘要： PURPOSE: To decrease the probability of delay in instruction read waiting decoding after branching by alllowing two times' share of branch destination instruction read of a branch instruction to have priority over other processings.
CONSTITUTION: The branch instruction is executed at the beginning of a cycle and the 1st instruction is read including a head instruction of branch destination. Since an FF12 goes to 1 during the cycle 2, a selector 16 selects an output line 34 of a register 6 and a selector 17 selects a fixed value 8 respectively. Further, 8 is added to the branch destination address by an adder 5 and the result is stored in the register 6. The content of the register 6 is transmitted to a storage device 1 on an address line 14 at the beginning of the next cycle 3 and the 2nd read instruction of the branch destination is attained. On the other hand, since an output of an FF11 goes to 1 when the decoding of the branch instruction is finished, an AND of a gate 30 is established, and a signal line 32 goes to 0. Thus, a decoding start command of the succeeding instruction is suppressed by a gate 29 and the start of next decoding is suppressed during the 2nd instruction is read.
COPYRIGHT: (C)1984,JPO&Japio
摘要翻译：目的：为了降低分支后的指令读取等待解码的延迟概率，将分支指令读取的分支目的地指令共享两次以优先于其他处理。构成：分支指令在一个周期的开始执行，第一个指令被读取，包括分支目的地的头指令。由于在周期2期间FF12变为1，所以选择器16选择寄存器6的输出线34，选择器17分别选择固定值8。此外，通过加法器5将8加到分支目的地地址，并将结果存储在寄存器6中。寄存器6的内容在下一周期3的开始时被发送到地址线14上的存储设备1 并且获得了分支目的地的第二读取指令。另一方面，由于当分支指令的解码结束时FF11的输出变为1，所以建立门30的AND，信号线32变为0.因此，解码开始命令后续指令被门29抑制，并且在读取第二指令期间抑制了下一个解码的开始。

4. 发明专利

JPS56129961A MONITOR SYSTEM FOR BRANCH INSTRUCTION 失效
公开(公告)号：JPS56129961A
公开(公告)日：1981-10-12
申请号：JP3157580
申请日：1980-03-14
申请人： HITACHI LTD
发明人： ABE SHIYUUICHI , KATOU MASAO , KATAOKA MASANORI
IPC分类号： G06F11/28 , G06F11/36
摘要： PURPOSE:To make easy to know which route of a program is tested or not yet tested, by analyzing the alternation career of instruction code of all the branch instructions on the program after the execution of program. CONSTITUTION:The operation code Bi of branch instruction is converted into Bix in advance and program is executed. The instruction having the Bix instruction code, changes the instruction code Bix to Biz on the memory when it is branched in addition to the branch instruction of the instruction code Bi, and changes to Biy when not branched. Next, when this branch instruction is executed, in case of the instruction code Biy, the instruction code on the memory is changed to the instruction code Bi of original branch instruction, with being branched in case of the instruction code Biy and without being branched in case of Biz. Further, in case of the instruction code Bi, the same operation as normal branch instruction Bi is made. Thus, after program is run, by retrieving the instruction code of the branch instruction in the program, which direction of the branch is scanned at least once is known relating to each branch instruction.

5. 发明专利

JPS5624645A DECIMAL MULTIPLICATION SYSTEM 失效
公开(公告)号：JPS5624645A
公开(公告)日：1981-03-09
申请号：JP10027579
申请日：1979-08-08
申请人： HITACHI LTD
发明人： ABE SHIYUUICHI , TAKEUCHI HIDENORI , HONMA KAZUYUKI
IPC分类号： G06F7/52 , G06F7/496 , G06F7/508 , G06F7/523 , G06F7/527
摘要： PURPOSE:To reduce the overhead and attain the high speed operation by providing a construction forming a multiplication decimal multiple at the time of requisition. CONSTITUTION:The content of the multiple corresponding portion of the multiple accommodating register 12 is read by the multiple reading register 2 and then the presence or absence of the multiple is tested. If the multiple is correctly read (in the case of forming the test condition), the content enters the multiplication loop and the contents of the intermediate result accommodating register 1 and the register 2 are added by 6 and the result thereof is obtained by the register 1. Then, the value of the register 1 is shifted by 8 rightward by one column and the one shifted out column is, for example, stored as the calculation result to complete the operation of one column. In the case when the required multiple is not yet calculated, (in the case when the test condition is not established), one multiple of the multiplier is read to the register 2 and after the required multiple is obtained to the register 3 by using the work resist 3 and the decimal adding circuit 6, it enters the multiplication loop and thereafter the calculation is progressed hereinafter similarly.

6. 发明专利

JPS60138642A INFORMATION PROCESSOR 失效
公开(公告)号：JPS60138642A
公开(公告)日：1985-07-23
申请号：JP24868183
申请日：1983-12-27
申请人： HITACHI LTD
发明人： WATABE SHINYA , ABE SHIYUUICHI
IPC分类号： G06F9/38
摘要： PURPOSE:To improve the instruction processing efficiency by holding the result of detection of an operand store comparison detecting circuit and rereading an operand immediately after the operand comparison is solved. CONSTITUTION:A store action end signal line 24 is set at 1 when all store actions are through after the execution of an instruction stored in a store register is started. In this case, a pointer line 25 shows (l) and a control line 27-l is set at 1 by a decoder 20. Then (m) units of OSC (Operand Store Comparison) latches 15-il are reset. Therefore, an OSC latch 15-kl is also reset and a line 28 is changed to ''0'' from ''1''. Then an operand rereading control circuit 18 which is so far kept under a waiting state is immediately executed.

7. 发明专利

JPS6063638A INFORMATION PROCESSOR 失效
公开(公告)号：JPS6063638A
公开(公告)日：1985-04-12
申请号：JP17112283
申请日：1983-09-19
申请人： HITACHI LTD
发明人： WATABE SHINYA , ABE SHIYUUICHI
IPC分类号： G06F9/38
摘要： PURPOSE:To detect OSC (operand storage compare) by obtaining the starting address and ending address of an operand processed in each decoding stage of a multidecoding instruction with 1B (byte) precision, and using those addresses. CONSTITUTION:When the starting address of the 1st memory operand is denoted as A1 and the starting address of the 2nd memory operand is denoted as A2 as to an instruction MVC which specifies, for example, two memory operands, an ending address (A1+7) is stored in an address increase latch 9 and an ending address (A1+L) of the 1st operand is stored in an address increase latch 11 as the 1st stage; and (A1+7) is stored in an upper-limit address register UAR13, and A1 is stored in a lower-limit address register LAR14. Then, the starting address and ending address of the 1st operand of the instruction MVC are obtained in the registers UAR13 and LAR14 through the 2nd and the 3rd stages.

8. 发明专利

JPS60129840A INFORMATION PROCESSING DEVICE 失效
公开(公告)号：JPS60129840A
公开(公告)日：1985-07-11
申请号：JP23950483
申请日：1983-12-19
申请人： HITACHI LTD
发明人： WATABE SHINYA , ABE SHIYUUICHI
IPC分类号： G06F9/38
摘要： PURPOSE:To minimize a disorder of a pipeline by constituting so that an operand by which a precedent instruction is changed is delivered by a byte unit without making it pass through a memory, to all following instructions to which pre- read of the operand has been executed. CONSTITUTION:A data is read out of a main storage device 5, and stored in one of an operand buffer register (OBR)14-1 or 14-2 through a data line 33. Before an execution of an instruction is started, the OBR14-1 or 14-2 designated by a control line 29 is selected by a selector 15, and stored in a data register (WAR)11. The WAR11 is a register by which a read-out operand is set when an execution of an instruction is started in an operating circuit 8, and an operation result of the operating circuit 8 is stored in a data register (WSR)10. The WSR10, the WAR11 and the OBRs 14-1, 14-2 have all an 8 byte width, and by providing a data path for delivering a store data stored in the WSR10, to the OBR14, it can be delivered without passing through a memory.

9. 发明专利

JPS6077241A INFORMATION PROCESSOR 失效
公开(公告)号：JPS6077241A
公开(公告)日：1985-05-01
申请号：JP18643783
申请日：1983-10-05
申请人： HITACHI LTD
发明人： WATABE SHINYA , ABE SHIYUUICHI
IPC分类号： G06F9/38 , G06F12/08
摘要： PURPOSE:To read out a branched instruction at a high speed and to improve instruction processing efficiency by forming a prefetching instruction change detecting logical part, and when the preceding instruction is changed, invalidating an instruction buffer and rereading an instruction from a memory. CONSTITUTION:The prefetching instruction change detecting logical part 4 compares an instruction reading address from a line 23 with a preceding storage address in which storage from a line 10 is incomplete and a storage address in executing to detect the presence of instruction data from a memory 2. If the instruction data is changed, the execution of the instruction is stopped by an instruction execution control part 32. A reset signal 22 is turned on by an instruction reading control part 9, the contents of a prefetching instruction buffer IBR5 are invalidated and instruction reading is started again. Consequently, the prefetching instruction change detecting logic can be prevented from omission and the high speed reading of the branched instruction and the improvement of the instruction processing efficiency can be attained.

10. 发明专利

JPS6027966A BUFFER STORAGE CONTROL SYSTEM 失效
公开(公告)号：JPS6027966A
公开(公告)日：1985-02-13
申请号：JP13724283
申请日：1983-07-27
申请人： HITACHI LTD
发明人： ABE SHIYUUICHI , KUBO KANJI , IZUMI CHIKAHIKO , WADA KENICHI , SHINTANI YOUICHI
IPC分类号： G06F9/38 , G06F12/08
摘要： PURPOSE:To realize the speeded-up pipeline processing of instructions which require by two memory operands by dividing a buffer storage device into a storage device dedicated to operands and a storage device used for fetching an operand and an instruction in common. CONSTITUTION:The buffer storage device consists of the 1st buffer storage device 10-1 dedicated to operands and the 2nd buffer storage device 10-2 for fetching an operand and an instruction in common, and the both storage devices are accessed independently of each other. The 2nd buffer storage device 10-2 is used normally for instruction fetch, but when an instruction requiring two memory operations at the same time is executed, the 2nd buffer storage device 10-2 is used for operand fetch as well as the 1st buffer storage device 10-1, and they are accessed at the same time to obtain the two memory operands at the same time. Thus, an operand and an instruction are fetched independently in parallel and the pipeline processing of the instruction which requires two memory operands is speeded up.

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