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1. 发明专利

JP2002237186A SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：JP2002237186A
公开(公告)日：2002-08-23
申请号：JP2001355488
申请日：2001-11-21
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： HORIGUCHI SHINJI , AOKI MASAKAZU , ITO KIYOO , NAKAGOME YOSHINOBU , IKENAGA SHINICHI , ETO JUN , MIYAKE NORIO , NODA TAKAAKI , TANAKA HITOSHI
IPC分类号： G11C11/407 , G05F3/24 , G11C11/401 , G11C29/00 , G11C29/12 , H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To stabilize operation of an internal voltage generating circuit. SOLUTION: This device has a first power source terminal and a second power source terminal for receiving external voltage, an internal voltage generating circuit generating internal voltage from the external voltage based on a potential supplied to the first power source terminal as reference, and an internal circuit operated making the internal voltage as a power source. The internal voltage generating circuit comprises a reference voltage generating circuit generating reference voltage formed based on a potential supplied to the first power source terminal as reference, and a drive circuit supplying the internal voltage formed based on the reference voltage to the internal circuit, the reference voltage generating circuit is arranged near the first power source terminal, while the drive circuit is arranged apart from the reference voltage generating circuit so that the drive circuit is made near the internal circuit, reference voltage outputted by the reference voltage generating circuit is supplied to the drive circuit by a wiring for distributing reference voltage. Thereby, compatibility of generating stable reference voltage and stabilizing a level of internal voltage is obtained.

2. 发明专利

JPS595658A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路设备
公开(公告)号：JPS595658A
公开(公告)日：1984-01-12
申请号：JP11389982
申请日：1982-07-02
申请人： Hitachi Ltd
发明人： MIYAKE NORIO , IWABUCHI MASARU
IPC分类号： H01L29/78 , H01L21/82 , H01L27/092 , H01L27/118
CPC分类号： H01L27/0927
摘要： PURPOSE:To make it possible to perform high speed operation, by forming gate electrodes and their wirings by a common high concentration polycrystal silicon layer, using the layer as a wiring between both cells, thereby reducing the wiring resistance especially at a wiring channel part. CONSTITUTION:Each gate electrode of both MISFETs 1 and 2 is formed by a common poly Si layer 15 with high concentration (e.g. 10 -10 /cm ). Said poly Si itself is extended as a wiring 5 and used for connecting opposing cell regions. When CMOS is manufactured (especially in a 3mum process), phosphorus treatment is performed on the entire surface after the poly Si for the gate electrodes is deposited. As this time, the entire poly Si layer is made to have high impurity concentration (an N electrode). Therfore, when P type impurities for forming source and drain regions of a P channel MISFET, e.g. of boron, are implanted at the next process, N type conductivity is held at high concentration in the poly Si gate electrode of said MOSFET.
摘要翻译：目的：为了能够进行高速运转，通过利用普通的高浓度多晶硅层形成栅极电极及其配线，可以将该层作为两个电池之间的布线，从而降低布线通道部分的布线电阻。构成：两个MISFET 1和2的每个栅极由具有高浓度（例如10 <14> -10 15 / cm 3）的普通多晶硅层15形成。所述多晶硅本身作为布线5延伸并用于连接相对的单元区域。当制造CMOS（特别是3μm工艺）时，在沉积用于栅电极的多晶硅之后，在整个表面上进行磷处理。此时，使整个多晶硅层具有高杂质浓度（N电极）。因此，当用于形成P沟道MISFET的源极和漏极区域的P型杂质时，例如，的硼在下一个工艺中被注入，在所述MOSFET的多晶硅栅电极中以高浓度保持N型导电性。

3. 发明专利

JPH03172782A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH03172782A
公开(公告)日：1991-07-26
申请号：JP31062989
申请日：1989-12-01
申请人： HITACHI LTD
发明人： MIYAKE NORIO
IPC分类号： G01R31/30 , G11C11/401 , G11C11/407 , H01L21/66 , H01L21/822 , H01L27/04
摘要： PURPOSE:To eliminate a dedicated terminal and to execute screening SC by constituting a device so that a reference voltage is increased in the case that a voltage impressed on a power source input terminal is over the maximum of a supply voltage varying range at the time of ordinary action. CONSTITUTION:When the supply voltage Vdd is set at 5V and the maximum of the varying range is set at 6V, for example, the logical threshold of an inverter 15 is set at 3V. Due to that, provided that the voltage impressed on the power source input terminal 6a is not more than 6V, the output potential of a noninversion amplifier circuit 9 is transmitted to an A/D converter 2 through a buffer amplifier circuit 10 as the reference voltage Vref. On the other hand, in the case that the voltage impressed on the terminal 6a is over the maximum of the varying range 6V and becomes 7V, for example, the voltage of 3.5V is impressed on the inverter 15 and the output state thereof becomes a high level. Besides, a MOSFET 14 in a voltage control means 17 is selectively turned on and an LSI 30 is made in an SC state. Then, the output potential of the circuit 9 is transmitted to the converter 2 through the circuit 10. That means, the state of the inverter 15 is automatically switched to the ordinary action state or the SC state by the voltage Vdd impressed on the terminal 6a.

4. 发明专利

JPH02244488A LARGE SCALE INTEGRATED CIRCUIT 失效
公开(公告)号：JPH02244488A
公开(公告)日：1990-09-28
申请号：JP6376489
申请日：1989-03-17
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： HORIGUCHI SHINJI , AOKI MASAKAZU , ITO KIYOO , NAKAGOME YOSHINOBU , IKENAGA SHINICHI , ETO JUN , MIYAKE NORIO , NODA TAKAAKI , TANAKA HITOSHI
IPC分类号： G11C11/413 , G05F3/24 , G11C11/401 , G11C11/407 , G11C11/409 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108
摘要： PURPOSE:To stabilize the operation by using two pieces of FETs of an enhancement type whose threshold voltages are different, fetching a voltage difference at the time when a current of a prescribed ratio is allowed to flow to them and setting it as a reference voltage. CONSTITUTION:This circuit consists of N channel MOSFETs Q61-Q63 and P channel MOSFETs Q64, Q65, and a positive voltage is applied from an external power source Vcc. In this case, the N channel MOSFETs Q61-Q63 consist of enhancement type FETs Q62, Q63 having a standard threshold voltage VTE and an enhancement type FET Q61 having a threshold voltage VTEE being higher than VTE. In such a way, since two pieces of FETs of an enhancement type whose threshold voltages are different are used, a difference of those threshold voltages can be made small enough. Accordingly, characteristics of two pieces of FETs can be fitted easily, and a stable reference voltage can be obtained. In such a way, the operation is stabilized.

5. 发明专利

JPH01296491A REFERENCE VOLTAGE GENERATING CIRCUIT 失效
公开(公告)号：JPH01296491A
公开(公告)日：1989-11-29
申请号：JP12574288
申请日：1988-05-25
申请人： HITACHI LTD
发明人： HORIGUCHI SHINJI , AOKI MASAKAZU , ITO KIYOO , NAKAGOME YOSHINOBU , MIYAKE NORIO , NODA TAKAAKI
IPC分类号： G11C11/407 , G05F3/24 , G11C11/34 , G11C11/409
摘要： PURPOSE:To obtain a circuit using no depletion type FET by defining potential difference generated when a constant current flows to two enhancement FETs, whose threshold voltages are different, as a reference voltage. CONSTITUTION:A mirror circuit 10 is formed by enhancement (EE) FETM4 and M5 and currents I1 and I2, which are determined by the constant ratio of the FETM4 and M5, flow and the current I2 is supplied to a standard EEFETM2, whose threshold voltage is a VTE and gate is connected with a drain. On the other hand, the current I1 flows to an EEFETM1, whose threshold voltage is higher than the voltage VTE and the FETM1-M3 are operated in a saturation area. Potential difference VR=VTEE-VTE in a nodal point between the FETM2 and M3 is extracted as a standard potential VR. Accordingly, it is not necessary to use the depletion type FET and the difference of the threshold voltage can be made small. Then, the stable reference voltage can be obtained by the EEFET to easily execute the matching of a characteristic.

6. 发明专利

JPS6364410A PCM CODE DECODER HAVING DIGITAL BALANCING CIRCUIT 失效
公开(公告)号：JPS6364410A
公开(公告)日：1988-03-22
申请号：JP20786986
申请日：1986-09-05
申请人： HITACHI LTD
发明人： OZAKI NAOHIKO , YAMAKIDO KAZUO , MIYAKE NORIO , NISHIHARA TATSUYA
IPC分类号： H03M1/00 , H04B3/03 , H04B3/20
摘要： PURPOSE:To suppress echo signals by concatenating the first balancing circuit for characteristic correction of a part corresponding to A/D, D/A converter etc. and the second balancing circuit having chraracteristic of a part corresponding to outside part from a PCM code decoder, and inserting the first balancing circuit between A/D, D/A converters by a controlling instruction. CONSTITUTION:Analog input signals from a telephone set are A/D converted 8 through a pre-analog circuit 7 and change 9 sampling frequency and coding form and output four-line digital signals from a terminal 11. Digital received signals inputted from a terminal 12 are subjected to similar digital processing 9, D/A converted 14, and outputted 16 through a back-end analog circuit 5 and supplied to a telephone set. A balancing circuit 19 is made to cascade connection of a balancing circuit 19a that approximates only characteristic of A/D, D/A converters and a balancing circuit 16b that approximates characteristic of only the circuit between 16-6, and a switch 22 is controlled by signals from a terminal 23. Replica of echo signals 18 made in the balancing circuit 19 is added 20 and canceled. By this constitution, output of echo signals to the terminal 11 can be suppressed nicely.

7. 发明专利

JPS6197972A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：JPS6197972A
公开(公告)日：1986-05-16
申请号：JP21848784
申请日：1984-10-19
申请人： Hitachi Ltd
发明人： MIYAKE NORIO
IPC分类号： H01L29/78 , H01L29/417
CPC分类号： H01L29/41775
摘要： PURPOSE:To prevent the fluctuations of threshold voltage by a method wherein the electrode being brought into contact with the semiconductor region, which is fixed at a constant potential, is made to interpose between the passivation film and the gate electrode through an insulating film. CONSTITUTION:An electrode 8 being brought into contact with a source region 3 is made to interpose between a passivation film 11 and a gate electrode 6 through a gate interlayer insulating film 7. Accordingly, such a trouble that the charge in the passivation film 11 shifts into an SiO2 film 5 when the package is sealed or at the time of the heat treatment process other than the sealing process of package and an effect is exerted on the amount of surface charge or the amount of interfacial surface charge is prevented by this electrode 8, while when the reference voltage circuit is actuated, the same potential as that of the source region is applied on the gate electrode. However, the effect of the potential is cancelled, because the potential of the source region is impressed on both of the two transistors, wherein a reverse conductive-type impurity to that of the gate region is introduced, for making the reference voltage generate and no effect is exerted on the generation of the reference voltage.
摘要翻译：目的：为了防止阈值电压的波动，通过绝缘膜将电极与固定为恒定电位的半导体区域接触的方法设置在钝化膜和栅电极之间。构成：与源极区域3接触的电极8通过栅极层间绝缘膜7插入钝化膜11和栅极电极6之间。因此，钝化膜11中的电荷偏移当封装密封时或在除封装的密封过程之外的热处理过程时成为SiO 2膜5，并且对表面电荷的量施加影响或通过该电极8防止界面表面电荷的量而当参考电压电路被致动时，与栅极电极相同的电位与源极区相同。然而，由于源极区域的电位被施加到两个晶体管的两个晶体管上，其中引入了与栅极区域的反向导电型杂质相反的导电型杂质，用于产生基准电压而没有对参考电压的产生产生影响。

8. 发明专利

JPS5962218A Digital-analog converter 失效
标题翻译：数字模拟转换器
公开(公告)号：JPS5962218A
公开(公告)日：1984-04-09
申请号：JP17086582
申请日：1982-10-01
申请人： Hitachi Ltd
发明人： MIYAKE NORIO , TSUJI MITSUO
IPC分类号： H03M1/74 , H03M1/66
CPC分类号： H03M1/66
摘要： PURPOSE:To obtain a D/A converter of a weight current system suitable for CMOS circuit integration by constituting a circuit so that the current consumption is decreased. CONSTITUTION:When an output of a gate circuit G0 is at high level, an analog switch SW01 is changed over to the position of an input capacitor 2C and an analog switch SW03 is turned off. Then, the output of an operational amplifying circuit A0 is a voltage equal to a reference voltage Vref. Since the output of a gate circuit G1 is at low level, since each analog switch SW remains said state, both input terminals of an operational amplifying circuit A1 are short-circuited, a voltage of a non-inverting input (+), an output Vref of a low-order digit is outputted as it is. When an output of the gate circuit G1 is at high level, an output of the operational amplifying circuit A1 is a voltage of 2 XVref. Thus, an analog voltage output after D/A conversion is obtained at the output of an operational amplifying circuit An of the most significant digit.
摘要翻译：目的：通过构成电路来获得适合于CMOS电路集成的重量电流系统的D / A转换器，从而降低电流消耗。构成：当门电路G0的输出为高电平时，模拟开关SW01切换到输入电容器2C的位置，模拟开关SW03截止。然后，运算放大电路A0的输出是等于参考电压Vref的电压。由于门电路G1的输出处于低电平，由于每个模拟开关SW保持所述状态，所以运算放大电路A1的两个输入端短路，同相输入（+）的电压，输出低位数的Vref被原样输出。当门电路G1的输出为高电平时，运算放大电路A1的输出为2×XVref的电压。因此，在最高有效位的运算放大电路An的输出端获得D / A转换后的模拟电压输出。

9. 发明专利

JPH0321110A GAIN CONTROL CIRCUIT 失效
公开(公告)号：JPH0321110A
公开(公告)日：1991-01-29
申请号：JP15455589
申请日：1989-06-19
申请人： HITACHI LTD
发明人： MIYAKE NORIO
IPC分类号： H03G3/02 , H03G3/10
摘要： PURPOSE:To obtain a gain control circuit capable of holding high accuracy and setting up gain up to a fine amplitude by means of a simple circuit by forming an attenuating circuit consisting of prescried resistor elements forming an 1/2 attenuation output from each output terminal. CONSTITUTION:The gain control circuit is constituted of ladder resistor circuits of R-2R. Each circuit is an attenuation circuit constituted so that resistor elements R, 2R forming 1/2 attenuation outputs from each output terminal are connected like a ladder in each output, and when an input signal Vin (V0) is inputted through an operational amplifier circuit OP1, the voltage of an output point V1 goes 1/2 the voltage V0 because the combined resistor value from the output point V1 up to ground potential is equal to R. Similarly, 1/2 the voltage of the point V1 is obtained from an output point V2, the same rule is applied hereinafter, and finally (1/2) the voltage of the signal V0 is obtained from an output point Vn. Thereby, attenuation value up to -42dB at maximum can be obtained with -6dB interval e.g. Since the resistor circuits whose resistance value ratios approximate to each other are used, a highly accurate attenuation value can be obtained by using a small occupied area.

10. 发明专利

JPH02245810A REFERENCE VOLTAGE GENERATING CIRCUIT 失效
公开(公告)号：JPH02245810A
公开(公告)日：1990-10-01
申请号：JP6612389
申请日：1989-03-20
申请人： HITACHI LTD
发明人： HORIGUCHI SHINJI , ETO JUN , AOKI MASAKAZU , ITO KIYOO , NAKAGOME YOSHINOBU , MIYAKE NORIO , NODA TAKAAKI
IPC分类号： G11C11/407 , G05F3/24 , G11C11/401 , G11C11/409 , H03K19/00
摘要： PURPOSE:To generate a stable voltage with less fluctuation due to an external power source voltage and a temperature by providing a current mirror means holding first and second currents flowing to in first and second FETs to be a constant rate and setting the potential difference of the inter-drain or the inter-source of first and second FETs to be a reference voltage. CONSTITUTION:P channel MOSFETs Q64 and Q65 share a gate and a source, and constitute what is called a current mirror circuit 70. It operates in such a manner that the rate of the drain current I1 of Q64 and the drain current I2 of Q65 becomes constant. The potential difference when the current of the constant rate is made to flow in FETs Q64 and Q65 is taken out and set to be the reference voltage. Since two FETs Q64 and Q65 different in a threshold voltage are used in an enhancement type, the difference of the threshold voltage can be set to be considerably small. Thus, the matching of the characteristics of two FETs is facilitated and the stable reference voltage can be obtained.

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