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1. 发明专利

JP2002237186A SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：JP2002237186A
公开(公告)日：2002-08-23
申请号：JP2001355488
申请日：2001-11-21
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： HORIGUCHI SHINJI , AOKI MASAKAZU , ITO KIYOO , NAKAGOME YOSHINOBU , IKENAGA SHINICHI , ETO JUN , MIYAKE NORIO , NODA TAKAAKI , TANAKA HITOSHI
IPC分类号： G11C11/407 , G05F3/24 , G11C11/401 , G11C29/00 , G11C29/12 , H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To stabilize operation of an internal voltage generating circuit. SOLUTION: This device has a first power source terminal and a second power source terminal for receiving external voltage, an internal voltage generating circuit generating internal voltage from the external voltage based on a potential supplied to the first power source terminal as reference, and an internal circuit operated making the internal voltage as a power source. The internal voltage generating circuit comprises a reference voltage generating circuit generating reference voltage formed based on a potential supplied to the first power source terminal as reference, and a drive circuit supplying the internal voltage formed based on the reference voltage to the internal circuit, the reference voltage generating circuit is arranged near the first power source terminal, while the drive circuit is arranged apart from the reference voltage generating circuit so that the drive circuit is made near the internal circuit, reference voltage outputted by the reference voltage generating circuit is supplied to the drive circuit by a wiring for distributing reference voltage. Thereby, compatibility of generating stable reference voltage and stabilizing a level of internal voltage is obtained.

2. 发明专利

JP2002111470A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2002111470A
公开(公告)日：2002-04-12
申请号：JP2000303493
申请日：2000-10-03
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： ASHIGA KOUICHI , NODA TAKAAKI , MASUJIMA KATSUHIRO
IPC分类号： G11C17/18 , G11C11/41 , G11C11/413 , G11C11/417 , G11C16/06 , G11C29/00 , G11C29/04 , H03K19/00 , H03K19/096
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device unnecessary of any added circuit such as a level conversion circuit for signal transmission inter circuit blocks having different operational power source voltages. SOLUTION: In the device, a semiconductor chip (1A) contains a plurality of circuit blocks (BLK1-BLK8) having different operational power source voltages and having a common logic threshold voltage, the blocks (BLK1-BLK8) treats a potential difference between a low voltage level and a high voltage level as an operational power source voltage, so that a signal output with an amplitude responding to the operational voltage with centering on the threshold voltage and a signal input with other amplitude with centering on the threshold voltage are available. Even though operational power source voltages of inner circuit blocks in the device are decided arbitrarily responding to operational frequencies of the blocks or switched responding to operational modes in programmable, the blocks can interface the signal output with the amplitude responding to the operational voltage with centering on a threshold voltage shared to each block without any needs of added circuit such as the level conversion circuit.

3. 发明专利

JP2002032422A SUPPORT SYSTEM FOR COMPONENT TABLE GENERATION 失效
公开(公告)号：JP2002032422A
公开(公告)日：2002-01-31
申请号：JP2000217230
申请日：2000-07-13
申请人： HITACHI LTD
发明人： MORIYAMA AKIRA , NODA TAKAAKI , KASHIWAGI MIHOKO , KAWAI YOSHIO
IPC分类号： G06F17/50
摘要： PROBLEM TO BE SOLVED: To provide a system which can easily generate a component table of good quality by selecting components in consideration of a combination of the components in a design upstream stage for a printed wiring board. SOLUTION: This system is provided with a circuit block database 16 stored with one or more components needed for a circuit constituting a function block on a printed wiring board and their total number, and the component table of good quality is easily generated at the design upstream stage by providing a component table editing part 11 which performs total number variation, addition, and deletion as to components for each circuit block, an alternative circuit block detection part 18 which detects an alternative circuit block for a nonstandard circuit block, and a circuit block substitution part 19 which substitutes components for each circuit block for component information taken out of a product design information master 15 managing design information on a printed wiring board, etc., having been designed.

4. 发明专利

JPH10134099A AUTOMATIC WIRING DESIGN SYSTEM 失效
公开(公告)号：JPH10134099A
公开(公告)日：1998-05-22
申请号：JP28792696
申请日：1996-10-30
申请人： HITACHI LTD
发明人： MURAMATSU MIHOKO , AONO MASAHIRO , TANAHASHI HIDEYUKI , ISONO MASAHIRO , NODA TAKAAKI
IPC分类号： H05K3/00 , G06F17/50
摘要： PROBLEM TO BE SOLVED: To design wiring in consideration of test performance so that all nets can be tested by deciding whether or not a test pad needs to be provided, selecting the section of the decided net, and generating a wiring pattern which makes the use of a through via hole essential for the section. SOLUTION: For the wiring design, a net to be wired is extracted (step 1). It is decided whether or not the extracted net needs to be provided with a test point (step 2). A section wherein through via hole use essential conditions are given is selected out of the sections constituting the extracted net (step 3). The use essential conditions of the through via hole are added to the selected section (step 4). Then when the through via hole use essential conditions are given to a wiring section, a wiring pattern using a through via hole is generated. Consequently, the wiring pattern need not be corrected to give a test pattern after wiring design, and all the nets are tested.

5. 发明专利

JPH0653758A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH0653758A
公开(公告)日：1994-02-25
申请号：JP22506092
申请日：1992-07-31
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： ASHIGA KOUICHI , NODA TAKAAKI
IPC分类号： H03F1/30 , H03F3/345 , H03F3/347
摘要： PURPOSE:To obtain the semiconductor integrated circuit provided with a buffer able to stably drive a device with a large capacity such as a personal computer or the like. CONSTITUTION:A constant current source M2 is provided to a drain of an input MOSFETM1 whose source receives an input voltage. A drain output of the input MOSFETM1 is fed to a gate of a source follower output MOSFETM3, an output voltage is obtained from the source and a constant current source M4 is provided to the source of the output MOSFETM3. Thus, the level shift quantity is set to zero based on a ratio of the size between the input MOSFETM1 and the output MOSFETM3 and a device with a large capacity such as a personal computer or the like is stably driven.

6. 发明专利

JPH02224508A BIAS CIRCUIT 失效
公开(公告)号：JPH02224508A
公开(公告)日：1990-09-06
申请号：JP4598589
申请日：1989-02-27
申请人： HITACHI LTD
发明人： NODA TAKAAKI
IPC分类号： H03F1/30
摘要： PURPOSE:To decrease the fluctuation in a bias current due to a temperature change by compensating a temperature dependency of a current for form a bias voltage with a reference voltage having a positive temperature characteristic outputted from a voltage generating circuit. CONSTITUTION:A voltage generating circuit 6 applies a reference voltage Vg12 having a positive temperature characteristic to a MOSFET Q12 of a current generating circuit 5. A current Is12 flows from the current mirror circuit comprising MOSFETs Q13, Q14 of the circuit 5 to MOSFETs Q15, Q16 having an equal threshold voltage and of two stages in series. Moreover, the current Is11 depends on the size of a current source Q11 and a voltage Vg12 and the size of the MOSFETs Q15, Q16 is multiplied by a multiple of four of that of the MOSFET Q12 and the current is independently of a power supply voltage and the threshold voltage. Thus, the temperature dependency of the bias current is decreased and the fluctuation in the bias current due to a temperature change is decreased.

7. 发明专利

JPS61169016A SIGNAL PROCESSING CIRCUIT 失效
公开(公告)号：JPS61169016A
公开(公告)日：1986-07-30
申请号：JP900885
申请日：1985-01-23
申请人： HITACHI LTD
发明人： NODA TAKAAKI
IPC分类号： H03K5/1252
摘要： PURPOSE:To eliminate noise without delay in signal detection by applying a pulse signal to a reset terminal and operating a counter circuit by a clock of a proper frequency to eliminate a pulse having a prescribed width or below as noise. CONSTITUTION:When the level of a dial pulse Pd applied to a reset terminal R of FF1-FF5 constituting a counter CNT changes from L to H, an output signal Pd' at an output terminal of the FF3 is changed to H, the counter CNT is reset while the level of the pulse Pd is at H and no count is executed. Thus, the counter CNT starts counting synchronously with a clock phic in 4kHz (period 0.25msec) and counts pulses up to 16 pulses, after 4msec (0.25msec X 16) is elapsed, the signal Pd' changes from H to L and the L level is maintained. The count is interrupted before the signal Pd' changes to L, and a high frequency noise having a width at least being

8. 发明专利

JPS6145627A Pulse generating circuit 失效
标题翻译：脉冲发生电路
公开(公告)号：JPS6145627A
公开(公告)日：1986-03-05
申请号：JP16637284
申请日：1984-08-10
申请人： Hitachi Ltd
发明人： NODA TAKAAKI , KOKUBO MASARU
IPC分类号： H03K7/08 , H02M7/48 , H03K5/01 , H03K5/04
摘要： PURPOSE: To attain pulse with modulation with different PWM characteristic by supplying selectively a reference voltage to be subtracted from an input voltage via a switch.
CONSTITUTION: A voltage proportional to a line current detected by an active L circuit AL is inputted to a subtraction circuit 2 as an input voltage Vin. A reference voltage Vr
1 or Vr
2 fed selectively via switches S
11 , S
12 from a reference voltage generating circuit 3 formed on the same board is inputted to the circuit 2. A voltage VL' outputted from the circuit 2 is fed to a noninverting input of a comparator C1. A sawtooth wave SW outputted from a sawtooth wave generating circuit 4 is fed to an inverting input via a voltage follower 5. The comparator C1 outputs an output voltage Vc
1 being at a low level only when the level of the sawtooth wave SW is higher than the voltage VL'.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：通过选择性地提供通过开关从输入电压减去的参考电压来获得具有不同PWM特性的调制脉冲。构成：与由有效L电路AL检测的线电流成比例的电压作为输入电压Vin被输入到减法电路2。通过开关S11，S12从形成在同一板上的基准电压产生电路3选择性地馈送的参考电压Vr1或Vr2被输入到电路2.从电路2输出的电压VL'被馈送到比较器的同相输入端 C1。从锯齿波产生电路4输出的锯齿波SW经电压跟随器5输入到反相输入端。比较器C1仅在锯齿波SW的电平高于电压VL'。

9. 发明专利

JP2000293565A DEVICE AND METHOD FOR GENERATING PATTERN CUT DIAGRAM OF PRINTED BOARD 失效
公开(公告)号：JP2000293565A
公开(公告)日：2000-10-20
申请号：JP10216899
申请日：1999-04-09
申请人： HITACHI LTD , HITACHI SOFTWARE ENG
发明人： NODA TAKAAKI , AONO MASAHIRO , NAKAKUMA SEIICHI , SOEJIMA YUICHI , TSUKADA SHIGEKI , SAITO KEIICHI
IPC分类号： H05K3/00 , G06F17/50 , H05K3/22
摘要： PROBLEM TO BE SOLVED: To avoid the case where a pattern cutting operation is carried out again after a pattern is once cut by deciding a noise countermeasure factor according to the signal type of a pattern cutting part and deciding automatically a pattern cutting position and the number of the pattern cutting is for the countermeasures of noises. SOLUTION: A noise countermeasure factor is decided according to the signal type of a pattern cutting part, and the pattern cutting position and the pattern cutting number are automatically decided. In this device, several pattern cutting positions and jumper wiring paths are indicated through the dialogs which are decided by a remodeled data dialog deciding part 46 on a pattern displayed on a screen. Then the data are sent to an automatic remodeled data deciding part 45 for other pattern cutting positions and jumper wiring paths. The part 45 refers to the cutting condition 4A, the parts information 4B and the net attribute information 4C to automatically decide the pattern cutting positions and jumper wiring paths.

10. 发明专利

JP2000011014A DEVICE AND METHOD FOR GENERATING JUMPER WIRING FIGURE 失效
公开(公告)号：JP2000011014A
公开(公告)日：2000-01-14
申请号：JP17558098
申请日：1998-06-23
申请人： HITACHI LTD
发明人： NODA TAKAAKI , AONO MASAHIRO , KASHIWAGI MIHOKO , SOEJIMA YUICHI , MURAYAMA YUKIJI , TSUKADA SHIGEKI , SAITO KEIICHI
IPC分类号： H05K3/00 , G06F17/50
摘要： PROBLEM TO BE SOLVED: To prevent wiring for a noise countermeasure again after executing jumper wiring by means of performing the countermeasure taking into consideration an electric noise of which a jumper wire receives by comparing an allowable wiring length corresponding to the signal of a route with the whole length of the route, judging it and designating a jumper wiring material in accordance with the judgement result. SOLUTION: The total sum of jumper wiring route segment lengths is calculated (S14). When the value exceeds an allowable wiring length which requires a noise countermeasure (S15) and also the noise countermeasure is not executed yet (S16), the search of FROM and TO points at a ground side is performed (S17) in order to execute noise countermeasure processing, for example, a twist pair-wiring with the ground. The search finds a pin or a buyer connected to the nearest ground making the signal side FROM points (or signal side TO points) as a base point. As the result, the ground side FROM and TO points against the signal side FROM and TO points are searched (S18). The wiring is ended since the whole jumper wiring routes are established (S19).

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