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1. 发明专利

JP2000331307A WRITE-IN COMPENSATING METHOD IN MAGNETIC RECORDING AND MAGNETIC RECORDING DEVICE 失效
公开(公告)号：JP2000331307A
公开(公告)日：2000-11-30
申请号：JP13676099
申请日：1999-05-18
申请人： HITACHI LTD
发明人： YAMAKAWA HIDEYUKI , NISHITANI TAKUJI , HIRAI TATSUYA , IDE HIROSHI , NARA TAKASHI , KOMATSU TATSUYA , TAKASHI TERUMI
IPC分类号： G11B5/09
摘要： PROBLEM TO BE SOLVED: To improve recording density further in a magnetic recording device using a MTR (3) code limiting continuous magnetization inversion to three times of the maximum. SOLUTION: Write-in compensation is performed at the time of recording data. A normal write-in pulse generates the write-in pulse lagging for a reference clock by a WPC1. For a pattern in which magnetization inversion is continued three times, in the first magnetization inversion, the write-in pulse is generated with the same timing as the reference clock, in the second, it is generated lagging by the WPC1, in the third, it is generated lagging by a WPC2. Consequently, an interval of the magnetization inversion in the pattern in which the magnetization inversion is continued three times is made wider, amplitude of a reproduced signal in the recording pattern is expanded.

2. 发明专利

JP2000114895A TRACK/HOLD AMPLIFIER 失效
公开(公告)号：JP2000114895A
公开(公告)日：2000-04-21
申请号：JP28236798
申请日：1998-10-05
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： ONO KOICHI , MATSUURA TATSUJI , IMAIZUMI SHIGEKI , HASE KENICHI , NARA TAKASHI
IPC分类号： H03F3/45 , H03G3/02
摘要： PROBLEM TO BE SOLVED: To provide a track/hold(T/H) amplifier capable of high-speed stable operation. SOLUTION: Concerning the T/H amplifier composed of a main T/H amplifier 31a for amplifying an analog signal and a replica control circuit 34a, the main T/H amplifier is composed of an MOS switch 24, capacitors C1 and C2, MOS differential pair M1 and M2 biased by a first voltage control current source 21, cascade transistors M3 and M4 for returning the output of this differential pair, load resistors R1 and R2 for output voltage generation and a second voltage control current source 26 for biasing the cascade transistors. The replica control circuit has the replica amplifier of the same circuit configuration as the main T/H amplifier and a feedback circuit composed of a resistor and an operational amplifier and supplies the operating point of a common mode, control voltage Vcmn and Vgain of gain to the main T/H amplifier. Thus, the stable T/H amplifier capable of independently controlling the gain and operating point can be provided.

3. 发明专利

JPH117736A METHOD AND APPARATUS FOR DETECTING ERROR, DECODING APPARATUS, AND, RECORDING REPRODUCING APPARATUS 失效
公开(公告)号：JPH117736A
公开(公告)日：1999-01-12
申请号：JP15842297
申请日：1997-06-16
申请人： HITACHI LTD
发明人： KATAYAMA YUKARI , NISHITANI TAKUJI , NARA TAKASHI , UEHARA YOICHI , NISHINA MASATOSHI
IPC分类号： G11B20/18 , H03M13/00
摘要： PROBLEM TO BE SOLVED: To improve error correction efficiency without increasing a byte length of an ECC when RLL(run length limit coded) recording data with the ECC(error-correcting code) added thereto are reproduced. SOLUTION: A reproduction signal is subjected to input signal process (P600) and ECC run length adjustment (P506). Moreover, the signal is subjected to RLL error detection (P505). As a result, it is judged whether the signal can be an RLL code. On the occasion of an ECC error correction (P507), a position of an error code detected at the RLL error detection is used as an erasure flag. Data after the ECC error correction are subjected to RLL decoding and further to CRC(cyclic redundancy code) error detection, whereby user data are generated.

4. 发明专利

JPH10261927A AGC CIRCUIT 失效
公开(公告)号：JPH10261927A
公开(公告)日：1998-09-29
申请号：JP6413797
申请日：1997-03-18
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： ONO KOICHI , MATSUURA TATSUJI , SONODA YASUHIRO , NARA TAKASHI
IPC分类号： H03G3/30
摘要： PROBLEM TO BE SOLVED: To provide an automatic gain control(AGC) circuit composed of high speed and high precision MOSs. SOLUTION: This circuit is composed of a variable gain amplifier whose a gain varies corresponding to a control voltage, an amplitude detector 71 and a charge pump circuit 72. In this case the amplitude detector 71 consists of two sets of preamplifiers 5a, 5b where one of input receives a common analog signal and another input part receives a reference voltage set at a prescribed voltage, two sets of differential pairs MN1-MN4 which output currents of noninverted and inverted outputs from a pair of output parts corresponding to an input difference voltage, loads MP1, MP2 that receive outputs of the differential pairs simultaneously and inverters INV1, INV2, and is provided with a means that connects each other the noninverting and inverting outputs of 2 sets of the differential pairs, extracts a current and flows the current to the loads. A charge pump circuit 72 is composed of a current source charging charges to a capacitor C, a current source discharging the charges, and MOS switches MP21-MP24 and MN21-MN24 controlled by one of control signals provided at both ends of each of the current sources.

5. 发明专利

JPH10134512A ADAPTIVE WAVEFORM EQUALIZER AND MAGNETIC DISK APPARATUS USING THE SAME 失效
公开(公告)号：JPH10134512A
公开(公告)日：1998-05-22
申请号：JP28245096
申请日：1996-10-24
申请人： HITACHI LTD
发明人： KUROSAWA MINORU , MIYAZAWA SHOICHI , HOTTA RYUTARO , HIROOKA TSUGUYOSHI , NARA TAKASHI
IPC分类号： G11B20/10 , H03H17/00 , H03H21/00 , H04B3/04
摘要： PROBLEM TO BE SOLVED: To provide a waveform equalizer by which the high speed and the stabilization of the optimization of a factor are made compatible. SOLUTION: An update circuit 68 performs an update processing operation in an update amount which is instructed from an update-amount selection circuit 67. At this time, a counting circuit 69 counts the number of times of a factor update operation. Then, when the number of times of the updata operation reaches the prescribed number of times of N, a control signal is sent to an averaging circuit 65 and to the update-amount selection circuit 67. Then, according to the signal, the averaging circuit 65 changes the number of times of an averaging operation (number of data) in an averaging processing operation, and it changes the frequency of the averaging processing operation, i.e., the frequency of the update operation. Actually, the frequency is made high at the initial stage of an optimization processing operation, and the frequency is made low after the update operation is performed the number of times of N. On the other hand, the update-amount selection circuit 67 changes over the decision method of the update amount from a proportional control system to a constant increment system.

6. 发明专利

JPH1022840A DIGITAL SIGNAL DECODER AND DECODING METHOD THERFOR 失效
公开(公告)号：JPH1022840A
公开(公告)日：1998-01-23
申请号：JP16897696
申请日：1996-06-28
申请人： HITACHI LTD
发明人： NISHITANI TAKUJI , YAMAKAWA HIDEYUKI , MIYAZAWA SHOICHI , MITA SEIICHI , UEHARA YOICHI , NARA TAKASHI , HIRANO AKIHIKO
IPC分类号： G11B20/18 , G11B20/10 , H03M13/23 , H03M13/41 , H04L25/497 , H03M13/12
摘要： PROBLEM TO BE SOLVED: To attain high-speed processing and to suppress complexity in the circuit for the decoder by selecting an alive path and a branch metric for each node from a metric of each node of a stage and adding a branch metric of each node to a metric of the alive path. SOLUTION: Captions C/S 26, 28 are arithmetic units for executing comparison/selection arithmetic operations. They compare four alive metric inputs and provide outputs of alive sequence pointers SM0-SM7 and also metrics M0 -M7 of each alive path selected newly. A SEL 61 selects any branch metric among the branch metric objects outputted from a BMU, according to the alive sequence pointers SM0-SM7. The selected branch metric is added to a metric of each node. The obtained result is fed back to a corresponding state, for the succeeding arithmetic cycle.

7. 发明专利

JPH09223365A DATA RECORDING AND REPRODUCING DEVICE 失效
公开(公告)号：JPH09223365A
公开(公告)日：1997-08-26
申请号：JP2892496
申请日：1996-02-16
申请人： HITACHI LTD
发明人： YAMAKAWA HIDEYUKI , NARA TAKASHI , TAKASHI TERUMI , NISHITANI TAKUJI
IPC分类号： G11B20/14 , G11B20/18 , H04L25/497
摘要： PROBLEM TO BE SOLVED: To inexpensively provide a recording and reproducing device using the EPRML system with higher accuracy in using the technology of the PRML system as it is by performing a specific decoding processing on a filter output obtained by precoding processing as exactly the same as the PRML system. SOLUTION: In this EPRML (EPR 4: expanding partial response class 4 and viterbi decoding system), the precoding processing 13 that is exactly the same as the PRML (partial response class 4 and viterbi decoding system) is performed from an encoder 11 to a filter 20. Now, output of the filter 20 is (1+D)-processed 21 to obtain output signal of the EPR 4. Then, viterbi decoding processing of 1/(1+D) is performed in a viterbi 22 and a decoder 12 to output a reproducing data. Thus, by using encoding and decoding technology, gain control technology and timing control technology in the PRML system as they are using the EPRML system higher than the PRML system in performance, the recording and reproducing device with higher accuracy is inexpensively provided.

8. 发明专利

JPH07212187A ACTIVE FILTER 失效
公开(公告)号：JPH07212187A
公开(公告)日：1995-08-11
申请号：JP436594
申请日：1994-01-20
申请人： HITACHI LTD
发明人： TANNO KOICHI , HOTTA RYUTARO , HASE KENICHI , KIMURA HIROSHI , WATANABE KUNIO , HIROOKA TSUGUYOSHI , NARA TAKASHI
IPC分类号： H03H11/10
摘要： PURPOSE:To suppress the fluctuation in the DC gain accompanying the change of the cutoff frequency of an active filter by adjusting an output resistance at the step where a device is tested in the shade of a wafer. CONSTITUTION:This filter is composed of variable gm amplifier circuits 41 and 42, capacity 45 and 46, current sources 47 and 48 for changing the value of gm, a variable load resistance circuit 43 and a variable negative resistance circuit 44. The resistance values of the default of the variable load resistance circuit 43 and the variable negative resistance circuit 44 are designed to the resistance values which are considered to be most proper. In this active filter, by adjusting the value of the variable load resistance circuit 43 or the variable negative resistance circuit 44 to proper values after the characteristic of actul DC gain is confirmed, the dispersion of elements composing the active filter and the fluctuation of the DC gain by a parasitic element are eliminated, and the fluctuation of the DC gain accompanied by the change of the cutoff frequency of the active filter can be suppressed.

9. 发明专利

JPH07115347A EQUALIZER FILTER 失效
公开(公告)号：JPH07115347A
公开(公告)日：1995-05-02
申请号：JP26063093
申请日：1993-10-19
申请人： HITACHI LTD
发明人： HASE KENICHI , HOTTA RYUTARO , WATANABE KUNIO , HIROOKA TSUGUYOSHI , KIMURA HIROSHI , TANNO KOICHI , NARA TAKASHI
IPC分类号： G11B5/09 , H03H11/04 , H03H11/12
摘要： PURPOSE:To improve S/N, and to prevent generation of a peak shift by providing an n-th order active band cut-off filter thereby optionally setting an attenuation characteristic in a high frequency band when a necessary equalizer characteristic is obtained. CONSTITUTION:A secondary differentiation circuit 1 functions as an equalizer for executing pulse slimming. An n-th order LPF 2 functions in order to eliminate a noise of a high frequency band. A primary HPF 3 is a primary differentiation circuit. A primary LPF 4 functions in order to fit a group delay characteristic to the primary HPF 3. The n-th order band eliminating filters(BEF) 5, 6 are constituted of two variable conductance circuits gm1-14, gm2-15, and two capacities C1-16, C2-17. By varying a value of a characteristic angular frequency of the BEFs 5, 6, an attenuation characteristic of the high frequency band can be varied.

10. 发明专利

JPH0765505A EQUALIZER CONTROL APPARATUS AND EQUALIZER CONTROL METHOD 失效
公开(公告)号：JPH0765505A
公开(公告)日：1995-03-10
申请号：JP21308293
申请日：1993-08-27
申请人： HITACHI LTD
发明人： KIMURA HIROSHI , HOTTA RYUTARO , HASE KENICHI , TANNO KOICHI , WATANABE KUNIO , HIROOKA TSUGUYOSHI , NARA TAKASHI , SHIRAISHI KAZUHISA
IPC分类号： G11B20/10 , H03G5/02 , H03K5/01
摘要： PURPOSE:To optimize waveform shaping process depending on a difference of recording and reproducing rates at the internal and external circumferences of a disk by simulating a transmission characteristic of an equalizer for processing the signal with the other equalizer equivalent to such a signal processing equalizer. CONSTITUTION:An equalizer for processing signals comprises a 2nd-stage LPFs and an amplifier for amplifying a signal depending on the preset boost amount. A control circuit 100 includes a control equalizer 5 of the structure equivalent to a signal processing equalizer 4 and a third LPF 7 equivalent to the LPF provided in the signal processing equalizer 4. A signal generator 6 oscillates at the cut-off frequency of LPF 7 and sends its oscillating signal to the control equalizer 5 and the third LPF 7. An amplitude difference detecting circuit 8 sets the boost amount of a boost amplifier of the signal processing equalizer 4 on the basis of a difference of output signals of the control equalizer 5 and third LPF 7.

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