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1. 发明专利

JPH04199320A DISK DRIVE CONTROL SYSTEM 失效
公开(公告)号：JPH04199320A
公开(公告)日：1992-07-20
申请号：JP33275290
申请日：1990-11-29
申请人： HITACHI LTD , HITACHI MICRO SOFTWARE SYST , HITACHI MICRO SYSTEM KK
发明人： YAMAZAKI YUKIE , SHIMADA YUJI , IZEKI TOSHIYUKI , HOCCHI YASUO , KIMURA SADAO , AKIMOTO OSAMU
IPC分类号： G06F3/06
摘要： PURPOSE:To shorten the average execution time of a command observed from a host side by parallelly executing data transfer between the host and buffer memory and data transfer between a disk drive device and the buffer memory to execute plural commands. CONSTITUTION:During executing the data transfer between a host 18 and a buffer memory 15 to execute one command, the data transfer between a disk drive device 13 and a buffer memory 15 for the other command execution or the seek processing of the disk drive device 13 are executed. In short, the restric tion for the combination of plural commands in a command queue is eliminated, and the data transfer between the host 18 and the buffer memory 15 and the data transfer between the disk drive device 13 and the buffer memory 15 are parallelly executed for executing plural commands. Thus, the average execution time of the command observed from the host 18 side can be shortened.

2. 发明专利

JPH03225673A DISK CONTROLLER 失效
公开(公告)号：JPH03225673A
公开(公告)日：1991-10-04
申请号：JP1905690
申请日：1990-01-31
申请人： HITACHI LTD , HITACHI MICRO SOFTWARE SYST
发明人： IZEKI TOSHIYUKI , MIYAZAWA SHOICHI , KURIHARA HIROSHI , HIROOKA TSUGUYOSHI , YAMAZAKI YUKIE , SHIMADA YUJI
IPC分类号： G06F3/06 , G11B20/10
摘要： PURPOSE:To execute high-speed data transfer for reproducing recorded data by processing the plural read data detected by a synchronizing bit detection circuit and writing the data from a FIFO to a shift register. CONSTITUTION:Read data RDT 1 and clocks RCLK1, RDT2 and RCLK2 synchronized to this data are respectively inputted from drives #1 and #2 to synchronizing bit detection circuits 11 and 12. The circuits 11 and 12 process the plural respective data, detect effective data and, thereafter output effective data D11 and D12 and respectively synchronized clocks C11 and C12 to FIFO 21 and 22. A read timing generation circuit 1 generates timing for transferring the data from the circuits 21 and 22 to shift registers 31 and 32. A byte clock generation circuit 2 generates a clock showing the data is completely stored into the registers 31 and 32. Thus, the data are stored into the FIFO 21 and 22 and written from the FIFO 21 and 22 to the registers 31 and 32 by inputting the bit clock of the circuit 1 and high-speed data transfer can be executed.

3. 发明专利

JPH05298237A 失效
公开(公告)号：JPH05298237A
公开(公告)日：1993-11-12
申请号：JP9929492
申请日：1992-04-20
申请人： HITACHI LTD , HITACHI MICOM SYST KK , HITACHI MICRO SOFTWARE SYST
发明人： KIMURA SADAO , AKIMOTO OSAMU , YAMAZAKI YUKIE , SHIMADA YUJI , HOCCHI YASUO
IPC分类号： G06F13/24 , G06F13/36
摘要： PURPOSE:To simplify an external access to a controller without keeping an access requester CPU in an idle state for a long period of time by canceling the access limitation in accordance with the processing state of an LSi and informing the CPU of the cancel of the access limitation by means of a trap interruption request. CONSTITUTION:When a CPU 1 has an access request to an SCSi controller 3, a flag register 62 is set. Meanwhile, a decoder 61 decides the propriety of the access. Then the register 62 is reset when the decoder 61 decides an access enable state to cancel the access inhibition and at the same time this cancel is informed by a trap interruption request INT. The CPU 1 knows the cancel of the access inhibition to the controller 3 with the request INT. Then, the CPU 1 can have an access to the automatic processing function of the controller 3 by means an access given to an I/F register 4.

4. 发明专利

JPH04355849A DISK CACHE DEVICE CONTROL SYSTEM 失效
公开(公告)号：JPH04355849A
公开(公告)日：1992-12-09
申请号：JP13096391
申请日：1991-06-03
申请人： HITACHI LTD , HITACHI MICRO SOFTWARE SYST
发明人： YAMAZAKI YUKIE , SHIMADA YUJI
IPC分类号： G06F12/08
摘要： PURPOSE:To raise the hit rate of a memory after the stop of rotation of a disk by reading data from a magnetic disk device to substitute ineffective data with valid data in the case of the existence of invalid data on a cache memory. CONSTITUTION:A magnetic disk cache controller 21 refers to contents of a cache directory 24 to discriminate whether each data on a cache memory 23 is valid or not, and the cache directory 24 is updated to contents corresponding to data on the cache memory when valid data is stored on the cache memory 23. If a false flag exists in validity/invalidity flag, the magnetic disk cache controller 21 sets the area address of a magnetic disk device 22, where data to be read is stored, to the disk logical block address of the row, whose validity/ invalidity flag is false, and stores read data in a cache block corresponding to this row in the cache directory 23 to make all data valid.

5. 发明专利

JPH0417045A DISK CACHE CONTROLLING SYSTEM 失效
公开(公告)号：JPH0417045A
公开(公告)日：1992-01-21
申请号：JP11983990
申请日：1990-05-11
申请人： HITACHI LTD , HITACHI MICRO SOFTWARE SYST
发明人： YAMAZAKI YUKIE , SHIMADA YUJI , HOCCHI YASUO
IPC分类号： G06F12/08 , G06F3/06 , G06F12/12
摘要： PURPOSE:To improve the hit ratio of a cache memory so as to reduce the accessing time to the cache memory by lowering the priority for leaving all one block data in the cache memory to the lowest level when an access request is made to all one block data from a host. CONSTITUTION:Whether an access request made from a host 21 is to all or partial one block data, with the one block being the minimum unit of managing a cache memory 25, is discriminated. When the access request is made to all one block data, the priority which leaves all one block data in the cache memory 25 is lowered to the lowest level. Namely, the priority is lowered to the lowest level, because the data remain in the main storage device on the host side when the host makes access to all one block data and the possibility of making access again to the data is low. Therefore, the hit ratio of the cache memory 25 can be improved.

6. 发明专利

JPH04205852A DISK CACHE DEVICE 失效
公开(公告)号：JPH04205852A
公开(公告)日：1992-07-28
申请号：JP32884490
申请日：1990-11-30
申请人： HITACHI LTD , HITACHI MICRO SOFTWARE SYST
发明人： YAMAZAKI YUKIE , SHIMADA YUJI , HOCCHI YASUO , SUZUKI YOSHITO
IPC分类号： G06F12/08 , G06F1/32 , G11B19/00
摘要： PURPOSE:To achieve a low power consumption by a method wherein, only at an erroneous hitting operation, a spindle motor for a magnetic disk is sctuated and wasteful consumption of electric power is reduced. CONSTITUTION:When a processing operation is started, a disk cache memory controller 203 turns off a spindle motor 211 by using a power-saving control 2. Together with this, a power supply for a signal processing circuit is turned off by using a power-saving control 1. Until a request comes from a host computer, the disk cache memory controller 203 is on standby in a low power consumption state. The low power consumption state refers to a state that, e.g. a clock which is input to the disk cache memory controller 203 is stopped so as to restrain wasteful consumption of electric power. Thereby, the low power consumption of the title device can be achieved.

7. 发明专利

JPH0451315A DATA TRANSFER SYSTEM 失效
公开(公告)号：JPH0451315A
公开(公告)日：1992-02-19
申请号：JP15977190
申请日：1990-06-20
申请人： HITACHI LTD , HITACHI MICRO SOFTWARE SYST
发明人： IZEKI TOSHIYUKI , HOCCHI YASUO , KURIHARA HIROSHI , SHIMADA YUJI , YAMAZAKI YUKIE
IPC分类号： G06F3/06
摘要： PURPOSE:To reduce the waiting for rotation to a half and to speed up the data transfer by saving data for showing a generation area and an exception factor, when the exception factor is generated in the course of data transfer, transferring the data of the remaining area, and thereafter, executing an exception processing. CONSTITUTION:In the case an error is generated as an exception factor in the course of this data transfer, a generation place storage processing 410 stores an address of an area to which the data transfer is executed at present, and data for showing the error cause or the kind in a storage part. Subsequently, by an area address decision processing 110, the decision is executed again. In the next defect area decision processing 112, in the case it is decided that a target area is a defective area, an alternate address storage processing 113 holds an address of an alternate area prepared in advance instead of the defective area. Next, in an exception processing end decision processing 411, whether an exception factor is generated in the course of area data transfer or not is decided by the generation place storage processing 410, and an exception processing 12 is executed.

8. 发明专利

JPH04205121A CURRENT CONTROL SYSTEM 失效
公开(公告)号：JPH04205121A
公开(公告)日：1992-07-27
申请号：JP32884690
申请日：1990-11-30
申请人： HITACHI LTD , HITACHI MICRO SOFTWARE SYST
发明人： YAMAZAKI YUKIE , HOCCHI YASUO , SHIMADA YUJI , MIYAZAWA SHOICHI
IPC分类号： G06F1/26 , G05F1/66 , H02J1/00
摘要： PURPOSE:To obtain the system which generates no over-load current without removing an incorporated module by holding the total system current consumption value below a rated current value by combining maximum current consumption values electric power of individual modules. CONSTITUTION:The maximum current consumption values and current values in current consumption suppression mode which are stored in ROMs 7, 21, and 31 on the modules 20-50 of the system are read out through a system bus 2. The system current consumption value is calculated from the total of the module current consumption values. In a current monitor sequence, the total system current consumption value is calculated before a mode is actually set according to a combination of current values in operation mode and the current consumption suppression modes. This calculated value is different from that in actual operation, but the actual value never exceeds the calculated value. Consequently, when the calculated value is less than the value of the rated current from the power source, the system stably operates.

9. 发明专利

JPH024549A CHARACTER PROCESSING SYSTEM 失效
公开(公告)号：JPH024549A
公开(公告)日：1990-01-09
申请号：JP15230888
申请日：1988-06-22
申请人： HITACHI LTD
发明人： IWAMOTO TETSUO , YAMAZAKI YUKIE , YAMAUCHI TSUKASA , MESE MICHIHIRO , MATSUDA YASUMASA
IPC分类号： B41J2/485 , G06F3/12 , G06K15/00 , G09G5/24
摘要： PURPOSE:To variously modify with a high quality by storing character profile information as a plurality of elements of contour line information for a character axis to be obtained, selecting it in response to a requested character width, dot-developing it, displaying and printing it. CONSTITUTION:A memory 101 stores, for example, character profile information corresponding to levels (character sizes) 81, 83, 85 of a character 'square' as contour profile lines 1-6. When a requested character width to be input from a keyboard 105 such as a target level value (64) 87 is requested, two nearest level values 83, 85 are selected, interpolated by a CPU 102, the contour line information representing the profile of a requested character is generated, dot-developed, displayed on a display 103, and printed by a printer 104. Thus, the character having the optimum character width for the character size can be displayed and printed.

10. 发明专利

JPH01318177A PROCESSING SYSTEM FOR VECTOR CHARACTER 失效
公开(公告)号：JPH01318177A
公开(公告)日：1989-12-22
申请号：JP15025688
申请日：1988-06-20
申请人： HITACHI LTD
发明人： YAMAZAKI YUKIE , IWAMOTO TETSUO , SUZUKI KAZUKO , YAMAUCHI TSUKASA , MESE MICHIHIRO
IPC分类号： G06T11/20
摘要： PURPOSE:To output characters having high quality and different line width from the outline information of a character by furthermore changing coordinate data based upon directiveness when vectors intersect with each other. CONSTITUTION:Coordinate data previously defined with directiveness are extracted from a keyboard 205 or a program in a storage device 201 and the coordinate values of vertexes constituting the outline of a character are changed to contract or expand the line width of the character. Then, the changed coordinate data are checked and the coordinate data of the intersecting vectors are changed again so as not to intersect. The current size is linearly changed to an objective character size by using the coordinate data and character dots are developed in a memory area specifying the data and outputted. Since a character having no void part can be outputted at the time of painting out the character, characters having high quality and different line width can be outputted from the outline information of one character.

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