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1. 发明专利

JPS62208491A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPS62208491A
公开(公告)日：1987-09-12
申请号：JP4840386
申请日：1986-03-07
申请人： HITACHI LTD , HITACHI VLSI ENG , HITACHI DEVICE ENG
发明人： YAMAGUCHI YASUNORI , YOSHIDA HIROHIKO , NEI MASAMI , ISHIHARA MASAMICHI , YAMAMOTO YUKIO
IPC分类号： G11C7/00 , G11C7/10 , G11C8/00 , G11C8/04 , G11C8/16 , G11C11/401
摘要： PURPOSE:To simplify a circuit and to improve a function by setting an initial value based on the output signal of a column decoder circuit and including a shift register forming the selection signal of a switch circuit for serial I/O due to the shift action of the initial value. CONSTITUTION:A complementary data line in a memory arrayes M-ARY0 and MARY1 connected to common data lines CD0 and CD1 through column switch circuits C-SW0 and C-SW1. A decode signal included in a column address signal supplied from the column decoder C-DCR in a serial transfer mode initializes the shift register SR (logic '1'), which executes a shift action. In that case signals of the M-ARY0 and M-ARY1 are outputted alternately in serial, and the common data liens CD0 and CD1 are linked to a random I/O output terminal D through a random I/O output circuit I/O and to a serial I/O output terminal Ds through a serial I/O circuit SIO. Thus a simple circuit can have a random I/O function and a serial I/O function.

2. 发明专利

JPS63261598A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPS63261598A
公开(公告)日：1988-10-28
申请号：JP9517987
申请日：1987-04-20
申请人： HITACHI LTD , HITACHI VLSI ENG , HITACHI DEVICE ENG
发明人： YAMAGUCHI YASUNORI , YOSHIDA HIROHIKO , NEI MASAMI , ISHIHARA MASAMICHI , YAMAMOTO YUKIO
IPC分类号： G11C11/41 , G11C11/34 , G11C11/401
摘要： PURPOSE:To simplify the constitution of a circuit by using a common column decoder circuit to produce a selecting signal for random input/output and an initial address for serial input/output respectively. CONSTITUTION:A signal route is provided for parallel transmission of signals to the data lines of memory arrays M-ARY0 and M-ARY1 as well as to latch circuits DFF0 and DFF1. While a switch route functions for connecting the circuits DFF0 and DFF1 to a common data line for serial input/output by means of a selecting signal produced by a shift register SR. At the same time, the output signal of a column decoder circuit C-DCR is supplied to each bit of the register SR as the initial value. Thus the circuit C-DCR is used in common for random input/output and serial input/output. As a result, both random input/ output and serial input/output are possible and at the same time the relevant circuit constitution can be simplified.

3. 发明专利

JPS61287097A TIMING GENERATING CIRCUIT 失效
公开(公告)号：JPS61287097A
公开(公告)日：1986-12-17
申请号：JP12820285
申请日：1985-06-14
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： KINOSHITA YOSHITAKA , NEI MASAMI
IPC分类号： G11C11/407 , G11C11/34
摘要： PURPOSE:To generate one timing signal of timing signals coming irregularly in order without a level loss and with high speed by using a transmission gate MOSFET controlled by one timing signal and controlling an output of the other timing signal. CONSTITUTION:The first timing signal phiop is supplied to a transmission gate MOSFET Q14 and to the gate of Q14, a power source voltage Vcc is supplied through a MOSFET Q13 receiving the second timing signal OE0. To one electrode of a booth trap capacity CB2 having the other electrode connected to the gate of Q14, a delay signal OE1 of the signal OE0 is supplied. When Q14 is operated by a high level of the signal OE0, the capacity CB2 is precharged, by the signal OE1, a gate voltage of Q14 is brought to a higher level than a power source voltage. Even when the two timing signals phiop and OE come irregularly, according to the delayed signal, an output timing signal phiop' is generated.

4. 发明专利

JPS61289596A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPS61289596A
公开(公告)日：1986-12-19
申请号：JP12982885
申请日：1985-06-17
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： YAMAGUCHI YASUNORI , NEI MASAMI
IPC分类号： G11C11/401 , G06F12/00 , G11C11/34
摘要： PURPOSE:To obtain a semiconductor memory device having many functions suitable for processing the highly speedy picture data by executing preferentially during a writing action only a mask setting set prior to the writing action of the writing signal supplied from an external terminal. CONSTITUTION:When the memory information of the memory cell is replaced to the writing signal supplied from the external terminal, in the function setting action, a pass signal ps is formed, and the writing signal through a data input circuit IB is transferred through a gate circuit G directly to the input output node of the memory part RAM instead of the logic operation circuit LU. An action mode to bypass the writing signal supplied from the external terminal is convenient when the optional picture element signal is replaced selectively to the signal from the external part. Consequently, when the special picture element is selectively replaced from the external terminal during the arithmetic action, by setting the automatic releasing function of the mask, without the new mask setting, the original arithmetic action can be continuously executed by setting the function only. Thus, the high speed of the picture processing can be realized.

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