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1. 发明专利

JPH0744729A ANIMATION GENERATION METHOD 失效
公开(公告)号：JPH0744729A
公开(公告)日：1995-02-14
申请号：JP21095593
申请日：1993-08-03
申请人： HITACHI LTD , HITACHI VLSI ENG , HITACHI TOHOKU SOFTWARE
发明人： TAKAHASHI HISASHI , YUURA KATSUHIKO , KUBO SHOICHI , SUGAWARA YASUHIRO
IPC分类号： G06F9/06 , G06F9/44 , G06T13/00 , G06T13/80
摘要： PURPOSE:To interactively and easily generate and change an animation program by which the change of an instance is screen displayed in an object directivity design support system. CONSTITUTION:This method is the animation generation method to define the parts of a device being a design object by the instance of an object directivity program on a computer, to make a user graphic correspond to the instance and to deform the display of the graphic interlocked with the operation of the instance on a computer. The animation method for designating the method argument of the method operating on the slot of the instance or on instance, for designating the graphic attribute of the user graphic and for setting/changing the graphic attribute of the user graphic by referring to the designated slot or method argument is automatically generated.

2. 发明专利

JPH04162668A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH04162668A
公开(公告)日：1992-06-08
申请号：JP28705890
申请日：1990-10-26
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： YAMANAKA TOSHIAKI , HASEGAWA NORIO , TANAKA TOSHIHIKO , HASHIMOTO KOJI , ISHIBASHI KOICHIRO , HASHIMOTO NAOTAKA , SHIMIZU AKIHIRO , SUGAWARA YASUHIRO , KURE TOKUO , IIJIMA SHINPEI , NISHIDA TAKASHI , TAKEDA EIJI
IPC分类号： G03F1/29 , G03F1/30 , G03F1/68 , H01L21/027 , H01L21/8244 , H01L27/11
摘要： PURPOSE:To enable wiring resistance to be reduced and a memory cell area to be reduced by placing a conductive film which fixes a source potential of a MOS transistor for drive at a reference potential on an upper part than the MOS transistor after covering an entire surface of the memory cell. CONSTITUTION:MOS transistors for driving an n channel T1 and T2 and MOS transistors T3 and T4 for transferring the n channel are formed within a p-type well 24 which is formed within an n-type silicon substrate 23. A connection hole 14c is opened on a high-concentration n-type impurities region 12c which becomes a common source of the MOS transistors T1 and T2. A second-layer conductive film 15c for fixing a source potential of all MOS transistors for drive within the memory cell is connected to the region 12c through the connection hole 14c, thus enabling a memory cell area to be reduced while reducing resistance of wiring resistor of the conductive film for fixing the source potential to the reference potential.

3. 发明专利

JPH0896020A SIMULATION CONTROL METHOD 失效
公开(公告)号：JPH0896020A
公开(公告)日：1996-04-12
申请号：JP23277794
申请日：1994-09-28
申请人： HITACHI LTD , HITACHI TOHOKU SOFTWARE , HITACHI VLSI ENG
发明人： SUGAWARA YASUHIRO , YUURA KATSUHIKO , TAKAHASHI HISASHI
IPC分类号： G06F17/50 , G06F17/00 , G06F19/00 , G06Q50/00 , G06Q50/10
摘要： PURPOSE: To quickly repeat from the construction of a model through the analysis and evaluation by designating an animation display range. CONSTITUTION: When an object capture procedure 303 is called, an interruption flag 311, a stop flag 306 and a skip flag 305 are referred to respectively. If these flags 311, 306 and 305 are set up, the interruption processing 309, the stop processing 308 and the skip processing 307 are carried out respectively. When the processing 307 is carried out, a graphic procedure 314 is not called out and a function procedure 317 is called out. Otherwise the procedure 314 is called. When the processing 308 is carried out, this processing is stopped before the procedure 314 is called. The simulation control processing is carried out based on the flag 311 when the processing 309 is called.

4. 发明专利

JP2001024169A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JP2001024169A
公开(公告)日：2001-01-26
申请号：JP19434099
申请日：1999-07-08
申请人： HITACHI LTD
发明人： IIJIMA SHINPEI , SUGAWARA YASUHIRO , FURUKAWA RYOICHI , YOSHIDA MASAYOSHI
IPC分类号： H01L27/108 , H01L21/8242
摘要： PROBLEM TO BE SOLVED: To prevent peeling at the oxidation reforming by using a poly-crystal tantalum oxide film as capacitor insulating film. SOLUTION: MISFET's Qs, Qn and Qp are formed on the major surface of a semiconductor substrate 1, a silicon nitride film 50 and a silicon oxide film 51 are deposited on a silicon oxide film 46, and lower electrodes 55 of titanium nitride, for example, are formed in holes 52. After that, a silicon nitride film is formed by an LPCVD method on the lower electrodes 55. Further, an amorphous tantalum oxide film is deposited by a CVD method and is heat treated in a non-oxidative atmosphere at 800 deg.C for 3 min. to form a poly-crystal tantalum oxide film 58. Further, the poly-crystal tantalum oxide film 58 is subjected to a heat treatment in an oxidative atmosphere such as ozone at 500 deg.C for 5 min. to correct the deficiency of oxygen in the poly-crystal tantalum oxide film 58.

5. 发明专利

JP2000049306A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JP2000049306A
公开(公告)日：2000-02-18
申请号：JP21359998
申请日：1998-07-29
申请人： HITACHI LTD
发明人： KANAI MISUZU , OJI YUZURU , FUKUDA TAKUYA , IIJIMA SHINPEI , FURUKAWA RYOICHI , SUGAWARA YASUHIRO , YAHATA HIDEJI
IPC分类号： H01L21/8242 , H01L21/02 , H01L21/8246 , H01L27/105 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To secure the high capacitance of a capacitor for memory by forming a capacitor part at the upper portion of a word line and a bit line and providing it over a memory cell. SOLUTION: A bit line 5 is formed, while being extended in the row direction of a MOS transistor and an insulation film 7 is formed at the upper portion. An SiO2 layer 12 is formed, a poly-Si layer is embedded into a recessed part 60 being sandwiched by the SiO2 layer 12, and the wall-shaped body of the poly-Si layer is used as one portion of the lower electrode of a capacitor. The comb-shaped pattern of the phosphorus-doped poly-Si layer 12 is cut by memory cells in a direction being in parallel with the word line. The memory cell is connected to a sensing amplifier by the bit line 5 and is connected to a word line driver by a word line, thus securing high integration and at the same time the high capacitance of a capacitor for memory.

6. 发明专利

JPS613209A OPERATION SYSTEM OF UNMANNED CARRIER 失效
公开(公告)号：JPS613209A
公开(公告)日：1986-01-09
申请号：JP12363884
申请日：1984-06-18
申请人： HITACHI LTD
发明人： MIURA MAKOTO , FUJIWARA TSUYOSHI , NISHINO SHIGERU , SUGAWARA YASUHIRO
IPC分类号： G05D1/02
摘要： PURPOSE:To easily cope with the alteration and extension of a conveyance layout by using a multiplex transmission device at a ground device side and a radio and an optical communication device between the ground device and guidance type unmanned carrier as the communication means of the guidance type unmanned carrier. CONSTITUTION:The unmanned carrier 21 is an optical guidance type carrier and runs along a reflective tape 23 as a line, and its destination and operation information are transmitted to the unmanned carrier 21 through an antenna 25 with a radio wave signal transmitted from the antenna 24 of a central controller 22. This carrier 21 is provided with a carrier controller 26, loading and unloading conveyor 27, and photoelectric switch 30 of the optical communication device. Further, a photoelectric switch 30 for transferring signals to and from said optical switch 28, a driving conveyor 31, and a terminal controller 32 are provided at a working shop 29. Consequently, conveyance patterns such as the calling, operation indication, etc., of the unmanned carrier 21 are specified optionally on a console panel and the line is easily changed.

7. 发明专利

JP2001044387A MANUFACTURE FOR SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JP2001044387A
公开(公告)日：2001-02-16
申请号：JP21307399
申请日：1999-07-28
申请人： HITACHI LTD
发明人： SUGAWARA YASUHIRO , IIJIMA SHINPEI , OJI YUZURU , YAMAMOTO NAOKI , FUKUDA NAOKI , JINBO TOMOKO , ISHII YUKINO , TANABE YOSHIKAZU
IPC分类号： H01L27/108 , H01L21/8242
摘要： PROBLEM TO BE SOLVED: To prevent a metal lower electrode of an underlayer from oxidizing, when annealing for modifying and crystallizing a high dielectric film composed of a crystalline metal oxide deposited in an upper part of the lower electrode of a capacity element constituted of a metal. SOLUTION: After a capacity insulting film structured of a tantalum oxide film 28 is deposited on the upper part of the lower electrode of a capacity element structured of a W film 26, annealing is connected in a hydrogen plus nitrous oxide mixed gas ambience, thereby restricting oxidization of the W film 26, while modifying and crystallizing the tantalum oxide film 28.

8. 发明专利

JPH11121713A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH11121713A
公开(公告)日：1999-04-30
申请号：JP28096397
申请日：1997-10-14
申请人： HITACHI LTD
发明人： NAKANISHI SHIGEHIKO , KOBAYASHI NOBUYOSHI , OJI YUZURU , IIJIMA SHINPEI , SUGAWARA YASUHIRO , KANAI MISUZU
IPC分类号： H01L27/108 , H01L21/02 , H01L21/314 , H01L21/316 , H01L21/8242 , H01L27/10 , H01L29/76 , H01L29/94 , H01L31/119
摘要： PROBLEM TO BE SOLVED: To secure the capacitance of the capacitor of the memory cells on and after 256 Mbit DRAM. SOLUTION: This semiconductor integrated circuit device is series-connected to the memory cell switching MISFETQs formed on the major surface of a semiconductor substrate 1, and the device includes a DRAM having a memory cell composed of an information storage capacitor C provided with a lower electrode 54, a capacitor insulating film 58 and an upper electrode 59. In this case, the lower electrode 54 is formed by the conductive material which is mainly composed of ruthenium dioxide (RuO2 ), and the capacitor insulating film 58 is formed by crystallized tantalum pentoxide.

9. 发明专利

JPH1126712A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, METHOD, AND DEVICE FOR MANUFACTURING THE SAME 失效
公开(公告)号：JPH1126712A
公开(公告)日：1999-01-29
申请号：JP17268497
申请日：1997-06-30
申请人： HITACHI LTD
发明人： IIJIMA SHINPEI , SUGAWARA YASUHIRO , OYU SHIZUNORI , ASANO ISAMU , TAMARU TAKESHI , KUNITOMO MASATO , NAKADA MASAYUKI , OJI YUZURU
IPC分类号： H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To reduce a leakage current of an information storage capacitance element. SOLUTION: A lower electrode 60 constituting an information storage capacitance element C is made of a polycrystal silicon film formed by solid phase crystallization of a deposited amorphous silicon film. A CMP method is used for working the lower electrode 60. A capacitance insulating film 61 constituting the information storage capacitance element C is made of a silicon nitride film and a polycrystal tantalum oxide film. The silicon nitride film is formed by a CVD method. The tantalum oxide film is formed by depositing an amorphous tantalum oxide film by a CVD method and then thermally treating the tantalum oxide film in an oxidative atmosphere. In addition, an upper electrode 62 constituting the information storage capacitance element C is made of a titanium nitride film formed by a CVD method. The intrinsic stress of the titanium nitride film is caused to be not more than 1 GPa.

10. 发明专利

JP2000058776A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JP2000058776A
公开(公告)日：2000-02-25
申请号：JP22882898
申请日：1998-08-13
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： SUGAWARA YASUHIRO , IIJIMA SHINPEI , OJI YUZURU , FURUKAWA RYOICHI , KANAI MISUZU , KUNITOMO MASATO , KURODA ATSUSHI , UEMURA TOSHIO
IPC分类号： H01L27/108 , H01L21/8242 , H01L21/8246 , H01L27/105
摘要： PROBLEM TO BE SOLVED: To increase the reliability and the degree of integration of a semiconductor device without reducing a storage capacity value of a capacitive element for storing information. SOLUTION: Capacitive elements C for storing information, each constituted of a lower electrode 54, a capacity insulation film 62, and an upper electrode 63, are serially connected to MISFETQs for selecting memory cells formed on a principal plane of a semiconductor substrate 1. A semiconductor integrated circuit device includes a DRAM having such capacitive elements C for storing information. The capacity insulation film 62 is a three-layer film constituted of a silicon oxide-nitride film 58 in contact with the lower electrode 54, a polycrystalline tantalum oxide film 57 having a crystal structure, and a silicon oxide film 60 in contact with the upper electrode 63.

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