专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JPS63267014A DIGITAL PHASE LOCKED LOOP CIRCUIT 失效
公开(公告)号：JPS63267014A
公开(公告)日：1988-11-04
申请号：JP9986287
申请日：1987-04-24
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： UEDA MASARU , KITAMURA NOBUAKI
IPC分类号： H03L7/06
摘要： PURPOSE:To improve the general-purpose application by setting switchingly a count bit number of a phase control counter. CONSTITUTION:A phase control counter 1 is constituted by providing a synchronous counter having flip-flop circuits whose number corresponds to the number of maximum count bits and which is set programmably as a major component and a gate means enabling a carrier forcibly to a carry to each flip-flop circuit of the post-stage in place of an output of the pre-stage, and the phase control of the output of the phase control counter 1 is applied through a lock time control circuit 4 executing the phase control when the degree of the shift of phase exceeds the threshold value based on the result of comparison by a phase comparator circuit 3. Thus, the degree of roughness or the maximum operating speed for the phase control is varied by controlling a gate means of the phase control counter 1 and the lock time of the phase control operation is controlled variably in response to the threshold value set to the circuit 4. Thus, the general-purpose application is improved remarkably.

2. 发明专利

JPS63240130A SYNCHRONOUS TYPE COUNTER 失效
公开(公告)号：JPS63240130A
公开(公告)日：1988-10-05
申请号：JP7150387
申请日：1987-03-27
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： UEDA MASARU , KITAMURA NOBUAKI
IPC分类号： H03K23/40 , H03K23/00 , H03K23/50 , H03L7/06
摘要： PURPOSE:To simplify the constitution and to quicken the count operation by providing a count-up control gate means controlling the count-up value into 0, +1, +2 based on a two bits control signal. CONSTITUTION:The phase control counter 1 applies the phase control of a count output with three kinds of count up values of 0, +1, +2 depending on supplied two bits phase control signals B1, B2. With the phase control signals of B1=0, B2=0 for example, the most significant bit count signal MSB and the carry signal CRY are kept to the initial state and the count-up value is made substantially zero. With the relation of B1=1 and B2=0, the count-up value is to be +1 and the normal operation is executed. Moreover, in case of B1=0, B2=1, the count-up value is to be +2. Thus, the maximum gate stage number is 4 to attain high speed count and the constitution is made simple by reducing the number of transistors being components of the phase control counter.

3. 发明专利

JPS63107255A NOISE SUPPRESSING CIRCUIT 失效
公开(公告)号：JPS63107255A
公开(公告)日：1988-05-12
申请号：JP25172486
申请日：1986-10-24
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： UEDA MASARU , KITAMURA NOBUAKI
IPC分类号： H03K5/1252 , H03K5/00 , H04L1/00 , H04L25/08
摘要： PURPOSE:To improve the noise discriminating characteristic by providing two shift registers, which transmit a reception digital signal synchronously with the leading edge and the trailing edge of a sampling clock signal, and a majority decision logic circuit which receives output signals consisting of a prescribed number of bits. CONSTITUTION:A noise suppressing circuit consists of two shift registers (flip flops FA1 and FA2 and flip flops FB1 and FB2) which shift a reception digital signal RD synchronously with the leading edge and the trailing edge of a sampling clock signal phis and the majority decision logic circuit which receives output signals having a prescribed number of bits from these shift registers and consists of AND gates AG1-AG6 and NOR gates NOG1 and NOG2. Thus, not only the reception digital signal which is in the high level for a time longer than the period of the sampling clock signal is surely transmitted as reception data but also the reception signal digital signal which is in the high level for a time equal to or shorter than a half period of the sampling clock signal phis is surely eliminated as noise.

你已经成功收藏专利！

检索式保存成功!

IPRDB