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1. 发明专利

JPS63293969A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS63293969A
公开(公告)日：1988-11-30
申请号：JP12832987
申请日：1987-05-27
申请人： HITACHI LTD , HITACHI TOBU SEMICONDUCTOR LTD , HITACHI MICROCUMPUTER ENG
发明人： OGURA SADAO , YAMAGUCHI TAKASHI , YAMAZAKI KOICHI , FUKUDA AKIROU , NAGUMO HIDEKARA , MORI SHUNJI , KAMEGAKI KAZUYUKI
IPC分类号： H01L27/04 , H01L21/822
摘要： PURPOSE:To improve the performance of an IC, and to enhance yield by forming all diffused resistors in the same block in a semiconductor device, in which a plurality of functional blocks are formed on a substrate and circuits including a plurality of the diffused resistors are formed into each block, along one direction on the main surface of the substrate. CONSTITUTION:Various functional blocks 2, 3... are disposed onto one main surface of one semiconductor chip 1, and these functional blocks represent a hand path-amplifier circuit 2, an APC (an auto-phase-control) circuit) 3, a power bias circuit 4, a cross processing circuit 5, etc. in an IC for a television, and circuits having correlation on characteristics such as an AMP 1, an AMP 2, an AMP 3, etc., are includ-. ed in one functional block 2. Accordingly, all resistors determining the characteristics of these circuits are arranged in the same direction in one functional block made up of the circuits having correlation on characteristics, thus acquiring correlation having high accuracy.

2. 发明专利

JPH01170039A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01170039A
公开(公告)日：1989-07-05
申请号：JP32709087
申请日：1987-12-25
申请人： HITACHI LTD , HITACHI TOBU SEMICONDUCTOR LTD , HITACHI MICROCUMPUTER ENG
发明人： OGURA SADAO , YAMAGUCHI TAKASHI , YAMAZAKI KOICHI , FUKUDA AKIROU , NAGUMO HIDETAKA , MORI SHUNJI , KAMEGAKI KAZUYUKI
IPC分类号： H01L27/04 , H01L21/822 , H01L27/08
摘要： PURPOSE:To cut down space of a resistor forming part in a linear IC, etc., thereby augmenting the integration by a method wherein the gaps between diffused layers of adjacent resistors are specified to be multiple types differentiated from one another in different positions. CONSTITUTION:The gap W' between two diffused resistors 2 (R1, R2) is specified to be, e.g., around 10mum in consideration of the expansion of depletion layers 3 and the errors in mask. On the other hand, adjacent diffusion resistors R3, R4 are parallel-connected on the parts of diffused layers or electrode parts at almost equivalent potentials so that the expansion of depletion layers, the MOS effect, etc., between resistor need not be taken into consideration enabling the resistor gap W2' to be specified narrower than the gap W1', e.g., 8mum. Through these procedures, the gap W2' between adjacent diffusion resistors R3, R4 at equivalent potentials can be specified narrower than the gap W1' between the adjacent diffusion resistors R1, R2 at different potentials so that the space may be cut down to make IC highly integrated without imperiling the functions of IC.

3. 发明专利

JPH01109761A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01109761A
公开(公告)日：1989-04-26
申请号：JP26643787
申请日：1987-10-23
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： KITAMURA YUKINORI , MORI SHUNJI , OGURA SADAO
IPC分类号： H01L27/04 , H01L21/316 , H01L21/318 , H01L21/822 , H01L21/8222 , H01L27/06
摘要： PURPOSE:To obtain high reliability and high density capacity, by using silicon nitride films having high moisture resistance and high relative permittivity as a protecting film for an active element and a dielectric film for a capacitor element at the same time. CONSTITUTION:A silicon oxide based first insulating film 7 is formed on the main surface of a semiconductor substrate 1. A silicon oxide based second insulating film 9 including phosphorous is formed on the first insulating film 7. The upper part of the second insulating film 9 in an active element region (a) and the first and second insulating films 7 and 9 in a capacitor element region (b) are selectively etched and a hole part 10A is formed. A silicon nitride based third insulating film 13, which has higher moisture resistance, higher heat resistance and relative permittivity higher than those of an SiO2 film, is formed on the hole part 10A. Thus, a protecting film for the active element region and an insulating film (dielectric film) for a capacitor in the capacitor element region are formed at the same time. Thus, high capacity is implemented and moisture resistance is improved. High reliability can be obtained for an IC, which is sealed with plastics.

4. 发明专利

JPH0374876A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0374876A
公开(公告)日：1991-03-29
申请号：JP21110489
申请日：1989-08-16
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： MAYUZUMI SHIRO , MORI SHUNJI
IPC分类号： H01L27/04 , H01L21/822 , H01L29/41
摘要： PURPOSE:To improve electrostatic breakdown withstand voltage by enlarging a connection hole area of an electrode at a terminating side for avoiding concentration of electric field generated here. CONSTITUTION:An n epitaxial layer 17 on a P type substrate 9 where an n layer 18 is embedded is separated by a P layer 2, an n island region is provided, and an n layer 22 and P layers 16 and 32 are formed. It is covered with an SiO2 film 1 and is suspended above connection holes 31 and 8 and connection holes 15 and 30 are formed on the P layer 16 and connection holes 31 and 8 are formed on the P layer 32. A hole diameter W2 of the connection hole 8 at the termination of a second resistor element R2 is increased to 4 to 5 times larger than the conventional value. A diameter W1 of the connection hole 15 at the starting terminal of a first resistor element R1 is reduced to a value which is equivalent to the other holes 30 and 31. With this configuration, when a positive electrostatic pulse is applied to a grounding potential from an I/O terminal 3 or a positive electrostatic pulse is applied to VCC from a terminal 3, concentration of electric field can be avoided and electrostatic breakdown withstand voltage is improved since the diameter W2 of the hole 8 of the R2 which transmits both pulses is made larger.

5. 发明专利

JPS63107162A VERTICAL TYPE PNP TRANSISTOR 失效
公开(公告)号：JPS63107162A
公开(公告)日：1988-05-12
申请号：JP25170686
申请日：1986-10-24
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： OGURA SADAO , YAMAZAKI KOICHI , TAKAHASHI KENJI , KITAMURA YUKINORI , MORI SHUNJI
IPC分类号： H01L29/73 , H01L21/331 , H01L27/08 , H01L29/72
摘要： PURPOSE:To obtain a transistor characterized by a small occupying area and an excellent current characteristic without a base-current compensating circuit, by forming a p type diffused layer, which is to become a collector, and a p layer, which is to become an emitter in alignment with said p type diffused layer, on the surface of an n-type semiconductor layer, and making a current to flow to the surface side from the inside of a substrate. CONSTITUTION:A p type Si substrate 11, an n embedded layer 12, a p embedded layer 13, a p embedded layer 14 and the like are provided. They are diffused at the same time as the n embedded layer 12 by ion implantation into the surface of the substrate 11. An n-type Si layer 15 is formed thereon by epitaxial growing. A p layer 16, which is to become an emitter lead-out part, and p isolation layers 17 are deeply diffused by simultaneous, selective ion implantation in the surface of the n-type epitaxial layer 15 and connected to the p embedded layers 13 and 14. A plurality of p layers 18, which are to become collectors, are formed over the p embedded layers as shallow diffused layers. A shallow n layer 19, which is to become a base lead-out part, is diffused. Thus multiple collectors are obtained in a small area, and a compact current mirror circuit device is implemented.

6. 发明专利

JPS6318659A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6318659A
公开(公告)日：1988-01-26
申请号：JP16189986
申请日：1986-07-11
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： KITAMURA YUKINORI , MORI SHUNJI , OGURA SADAO , YAMAZAKI KOICHI , INABA TORU
IPC分类号： H01L27/04 , H01L21/331 , H01L21/337 , H01L21/822 , H01L29/73 , H01L29/732 , H01L29/808 , H01L29/8605
摘要： PURPOSE:To make the resistance value easy to set and variable, by providing electrodes in a first layer of second-conductivity type and a second layer of second-conductivity type, and providing other two electrodes, which hold the second layer of second- conductivity type in the first-conductivity type substrate surrounded by the first layer of second-conductivity type and an embedded layer. CONSTITUTION:On an p type Si semiconductor substrate 1, an n type Si layer 2 is formed by epitaxial growing. An n embedded layer 3 is buried between the substrate 1 and the layer 2. P embedded layers 4 and 5 are formed by implanting p type impurity ions in the surface of the substrate 1 and diffusing the ions in the n-layer after the formation of the epitaxial n layer. A p diffused layer 6 is formed by partially implanting and diffusing ions from the surface of the epitaxial (n) layer. The layer is connected to the embedded layers 4 and 5, and element isolating layers 6 and 5 are formed. A (p) diffused layer 7 is formed on the surface of an (n) layer 2 ', which is to become a resistor region. n diffused layers 8 and 8 are made to be electrode lead-out parts. Thus, the resistor, in which the resistance value can be readily set, and which can be used as a variable resistor by the application of a voltage to the diffused layer 7, can be provided.

7. 发明专利

JPH0322468A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH0322468A
公开(公告)日：1991-01-30
申请号：JP15749189
申请日：1989-06-19
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： KITAMURA YUKINORI , OGURA SADAO , MAYUZUMI SHIRO , MORI SHUNJI , FUKAMACHI TOSHIYUKI , KOBAYASHI YUJI , YAMAZAKI KOICHI , FURUHATA MAKOTO , KAMEGAKI KAZUYUKI
IPC分类号： H01L21/761 , H01L21/822 , H01L21/8222 , H01L21/8226 , H01L27/02 , H01L27/04 , H01L27/06 , H01L27/082 , H04N9/79
摘要： PURPOSE:To improve component density of a semiconductor integrated circuit device used in color VCR by a method wherein a luminance signal processing element and a color signal processing element of the VCR are constructed in different areas of the main surface of a semiconductor substrate respectively and an isolating zone supplying a stable bias on an alternating-current basis is constructed between the luminance signal processing element and the color signal processing element on the main surface of said semiconductor device. CONSTITUTION:A luminance signal processing element 11 and a color signal processing element 12 of color VCR 1 are mounted on one semiconductor integrated circuit device(IC) 10. In other words, the luminance signal processing element 11 and the color signal processing element 12 are formed monolithic. This semiconductor integrated circuit device 10 is mounted on a resin-sealed type semiconductor device 20. The semiconductor integrated circuit device 10 divides each of the luminance signal processing element 11 and the color signal processing element 12 is two substantially and each element divided in two vertically is disposed with the central part used as the boundary. In the resin-sealed type semiconductor device 20, a 41st terminal is disposed between the luminance signal processing element 11 and the color signal processing element 12 and a direct-current reference power being stable on an alternating-current basis is impressed thereon. The area of a shared part can be lessened much, in particular, by forming the elements in one chip, and thus the component density can be improved.

8. 发明专利

JPS6318657A LAMINATED RESISTOR ELEMENTS AND SEMICONDUCTOR DEVICE USING SAME 失效
公开(公告)号：JPS6318657A
公开(公告)日：1988-01-26
申请号：JP16190186
申请日：1986-07-11
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： KITAMURA YUKINORI , MORI SHUNJI , OGURA SADAO , YAMAZAKI KOICHI , TAKAHASHI KENJI
IPC分类号： H01L27/04 , H01L21/822 , H01L27/08
摘要： PURPOSE:To improve integration density, by providing an isolating layer between a semiconductor element and three layers of resistor elements, and forming a third resistor element by an electrode lead-out layer, which is formed together with an embedded layer that is embedded in a semiconductor substrate and the isolating layer. CONSTITUTION:An epitaxial n type Si layer 12 is formed on a p type Si substrate 11. An n type embedded layer 13 is diffused by implanting ions of Sb and the like in the surface of the substrate 11. A p type embedded resistor 14 is formed by implanting B ions in the surface of the substrate 11 including the n embedded layer and diffusing the ions in the layer 12, which is grown thereon. A p diffused layer 15 is formed by ion implanting diffusion using the isolation process from the surface of the epitaxial (n) layer so that the layer 15 is connected to the resistor 14. Electrodes 17 and 17 are provided on the diffused layers 15 and 15. The layer 12 is connected to a potential Vcc. A p diffused resistor 16 is formed by shallow ion implantation and diffusion in the surface of the epitaxial (n) layer. Electrodes 18 and 18 are provided at both ends of the reistor 16. Thus the resistors 14 and 16 can be formed at a high integration density.

9. 发明专利

JPH02143453A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH02143453A
公开(公告)日：1990-06-01
申请号：JP29595888
申请日：1988-11-25
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： MORI SHUNJI , KITAMURA YUKINORI
IPC分类号： H01L27/095 , H01L21/8222 , H01L21/8226 , H01L21/8248 , H01L27/06 , H01L27/082
摘要： PURPOSE:To increase throughput in a manufacturing line, and reduce cost by separately forming the base of an NPN transistor and the P-channel region of a P-channel junction type FET, and simultaneously forming the emitter of the NPN transistor and the upper gate of the P-channel junction type FET. CONSTITUTION:An N buried layers 2a-2c, and a P isolation layer 4a are formed on the surface layer part of a substrate 1; an N epitaxial layer 3 is formed on the whole surface; a P semiconductor region 5 turning to the intrinsic base of an inverse NPN transistor(TR), and a P semiconductor region 9 turning to the P-channel region of a junction type FET are formed; N semiconductor regions 13, 3c and 3a, 6 turning to be emitter leading out ports and collector leading out ports of the NPN Tr and the inverse Tr, and N type semiconductor regions 10, 3b turning to be upper gate leading out ports and lower gate leading out ports of the junction type FET are simultaneously formed. By this method, throughput is increased and cost can be reduced.

10. 发明专利

JPS6318671A SEMIOCNDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPS6318671A
公开(公告)日：1988-01-26
申请号：JP16190086
申请日：1986-07-11
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： KITAMURA YUKINORI , MORI SHUNJI , OGURA SADAO , TAKAHASHI KENJI , YAMAZAKI KOICHI
IPC分类号： H01L29/73 , H01L21/331 , H01L27/08 , H01L29/72 , H01L29/732
摘要： PURPOSE:To obtain a semiconductor device characterized by a large base width of a p-n-p transistor, small dispersion in hFE and a small area of an element, by forming a p-type layer, which becomes an emitter, so that the diffusing depth of said layer is shallower than the depth of a p-type layer, which becomes the base of an n-p-n transistor. CONSTITUTION:An n Si layer 2 is formed on a substrate by epitaxial growing. An n embedded layer 3 is buried in the layer 2. A p embedded layer 4 is buried in a part of the layer 2. B ions are partially implanted, and a p layer 6 is connected to a p embedded layer 5. A collector lead-out p layer 12 of a p-n-p transistor TR is connected to the layer 4. Then, P and B ions are implanted, and a collector lead-out n layer 7 and a base p layer 8 are formed. Then, an emitter n layer 9 is diffused by implanting As ions. At the same time, an n layer 11 for base lead-out part is formed. B ions are implanted to a shallow part in order to form said emitter and diffused. A p-type layer 13 is formed. A shallow highresistance p-type layer 14 is formed in the same process. Contact holes are provided in the surface oxide film. An Al electrode is formed by the evaporation of Al, annealing and patterning.

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