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    • 10. 发明专利
    • VERTICAL TYPE PNP TRANSISTOR
    • JPS63107162A
    • 1988-05-12
    • JP25170686
    • 1986-10-24
    • HITACHI LTDHITACHI MICROCUMPUTER ENG
    • OGURA SADAOYAMAZAKI KOICHITAKAHASHI KENJIKITAMURA YUKINORIMORI SHUNJI
    • H01L29/73H01L21/331H01L27/08H01L29/72
    • PURPOSE:To obtain a transistor characterized by a small occupying area and an excellent current characteristic without a base-current compensating circuit, by forming a p type diffused layer, which is to become a collector, and a p layer, which is to become an emitter in alignment with said p type diffused layer, on the surface of an n-type semiconductor layer, and making a current to flow to the surface side from the inside of a substrate. CONSTITUTION:A p type Si substrate 11, an n embedded layer 12, a p embedded layer 13, a p embedded layer 14 and the like are provided. They are diffused at the same time as the n embedded layer 12 by ion implantation into the surface of the substrate 11. An n-type Si layer 15 is formed thereon by epitaxial growing. A p layer 16, which is to become an emitter lead-out part, and p isolation layers 17 are deeply diffused by simultaneous, selective ion implantation in the surface of the n-type epitaxial layer 15 and connected to the p embedded layers 13 and 14. A plurality of p layers 18, which are to become collectors, are formed over the p embedded layers as shallow diffused layers. A shallow n layer 19, which is to become a base lead-out part, is diffused. Thus multiple collectors are obtained in a small area, and a compact current mirror circuit device is implemented.