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1. 发明专利

JP2001210620A SEMICONDCUTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 失效
公开(公告)号：JP2001210620A
公开(公告)日：2001-08-03
申请号：JP2000013714
申请日：2000-01-24
申请人： HITACHI LTD , HITACHI TOBU SEMICONDUCTOR LTD
发明人： KUROKAWA ATSUSHI , NAKANISHI MASAKI , IMAMURA YOSHINORI , YAMANE MASAO
IPC分类号： H01L21/302 , H01L21/301 , H01L21/3065
摘要： PROBLEM TO BE SOLVED: To enable a joint between adjacent semiconductor chips which are jointed mechanically together to be enhanced in mechanical strength. SOLUTION: A first bonding member 9 is formed on the surface of a semiconductor substrate 1 between semiconductor chips adjacent to each other, so as to surround all the periphery of the semiconductor chips, and the adjacent semiconductor chips are jointed mechanically together through the intermediary of the first bonding member 9.

2. 发明专利

JPH0964063A GALLIUM ARSENIDE SEMICONDUCTOR ELEMENT 失效
公开(公告)号：JPH0964063A
公开(公告)日：1997-03-07
申请号：JP21430595
申请日：1995-08-23
申请人： HITACHI LTD
发明人： SASAKI KENJI , NAGAI HIROYUKI , YAMANE MASAO
IPC分类号： H01L21/301 , H01L21/338 , H01L29/812
摘要： PROBLEM TO BE SOLVED: To enhance the reproducibility of a threshold value by inclining the gate lengthwise direction of a gallium arsenide semiconductor element having a field effect transistor formed at the periphery by a cleavage with respect to a cleavage line. SOLUTION: A GaAs power FET is formed on the plane (100) of a semi- insulating GaAs substrate. The right end face of a gallium arsenide semiconductor element 1 of a cleaved surface becomes, for example, a plane (0-1-1), and the front surface becomes a plane (010-1). The angle of the extending direction of a gate finger 5 has a predetermined angle θ with respect to the one plane (0-1-1) of one of the peripheries of the element 1. Accordingly, the direction 6 of the finger 5, i.e., the gate lengthwise direction perpendicular to the lengthwise direction has a predetermined angle θ with respect to the plane (010-1) of one of the peripheries of the element 1 since the element 1 is rectangular.

3. 发明专利

JP2564296B2 失效
公开(公告)号：JP2564296B2
公开(公告)日：1996-12-18
申请号：JP6882387
申请日：1987-03-25
申请人： HITACHI LTD
发明人： USAGAWA TOSHUKI , YAMANE MASAO , HIRUMA TAKEYUKI , MISHIMA TOMOYOSHI
IPC分类号： H01L29/73 , H01L21/331 , H01L21/338 , H01L29/205 , H01L29/72 , H01L29/737 , H01L29/778 , H01L29/80 , H01L29/812

4. 发明专利

JP2559412B2 失效
公开(公告)号：JP2559412B2
公开(公告)日：1996-12-04
申请号：JP15328787
申请日：1987-06-22
申请人： HITACHI LTD
发明人： YAMANE MASAO , MISHIMA TOMOYOSHI , SASAKI YOSHIMITSU , KOBAYASHI MASAYOSHI , USAGAWA TOSHUKI , TAKAHASHI SUSUMU
IPC分类号： H01L29/205 , H01L21/338 , H01L29/778 , H01L29/80 , H01L29/812

5. 发明专利

JPH0870245A LOW DISTORTION SWITCH 失效
公开(公告)号：JPH0870245A
公开(公告)日：1996-03-12
申请号：JP20319094
申请日：1994-08-29
申请人： HITACHI LTD
发明人： TANAKA SATOSHI , OKAMOTO TATSUTO , KITAYAMA TARO , YAMANE MASAO
IPC分类号： H01P1/15 , H03K17/06 , H03K17/16 , H03K17/687 , H03K17/693
摘要： PURPOSE: To provide a high frequency switch with a low distortion characteristic operatable at a low voltage by composing a passing field effect transistor(FET) on the reception side of a dual gate FET and grounding FET on the transmission side and connecting a capacitors between the 1st gate and source and between the 2nd gate and a drain. CONSTITUTION: A dual gate FET is adopted for a receiver side passing field effect transistor(FET) 2 and a sender side grounding FET 4 in an SPDT(single- pole double throw) switch comprising FETs, and a capacitor is connected between a 1st gate (source side gate) and a source and between a 2nd gate and a drain. Thus, an amplitude of an AC signal generated in the 2nd gate is increased by adding the capacitor between the 2nd gate and the drain so that the turning on of the FET is prevented when the signal rises negatively and an amplitude of the AC signal generated in the 1st gate is increased by adding the capacitor between the 1st gate (source side gate) and the drain so that the turning on of the FET is prevented when the signal rises positively.

6. 发明专利

JPH04206740A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH04206740A
公开(公告)日：1992-07-28
申请号：JP33708790
申请日：1990-11-30
申请人： HITACHI LTD
发明人： TANIMOTO TAKUMA , YAMANE MASAO , GOSHIMA SHIGEO , UCHIDA YOKO , UMEMOTO YASUNARI
IPC分类号： H01L27/095 , H01L21/203 , H01L21/338 , H01L29/778 , H01L29/812
摘要： PURPOSE:To acquire a complementary FET having both characteristics of a P-channel FET and an N-channel FET by forming a P-channel layer to a distortion layer whose lattice constant is larger than that of a layer which is adjacent to an opposite side of an electrode against the P-channel layer. CONSTITUTION:In a semiconductor device having both a P-channel semiconductor device and an N-channel semiconductor device, a P-channel layer 7 is made a distortion layer whose lattice constant is larger than a layer 6 which is adjacent to an opposite side of an electrode against the P-channel layer 7. For example, an AlxGa1-xAs layer 2, an n-InyGa1-yAs layer 3, an AlxGa1-xAs layer 4, a GaAs layer 5, an AlxGa1-xAs layer (x=0.45) 6, an InyGa1-yAs layer (y=0.2, 15nm) 7, an AlxGa1-xAs layer 8, a p-AlxGa1-xAs layer 9, an AlxGa1-xAs layer 10, a p -GaAs layer 11, an AlxGa1-xAs layer 12 and a GaAs layer 13 are formed on a semiinsulating GaAs substrate 1 by MBE device; then, lastly, a p -GaAs layer 14 is deposited thereon. Thereafter, isolation, etc., by mesa etching is carried out.

7. 发明专利

JPH0258339A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH0258339A
公开(公告)日：1990-02-27
申请号：JP20831388
申请日：1988-08-24
申请人： HITACHI LTD
发明人： KOBAYASHI MASAYOSHI , YAMANE MASAO , TAGAMI TOMONORI , TAKAHASHI SUSUMU
IPC分类号： H01L29/205 , H01L21/338 , H01L29/778 , H01L29/812
摘要： PURPOSE:To form an electrode pattern without newly providing a spacer layer using a cap layer as a spacer layer at the time of formation of an electrode by a lift-off method. CONSTITUTION:After an N type GaAs layer is laminated on a nondoped Al0.3 Ga0.7As layer, an N type GaAs cap layer which operates as a spacer layer is etched. Since a dry etching work has strong anisotropy, the worked shape of an N type GaAs layer 6 becomes substantially the same size as those of the openings of photoresists 8, 10 at the initial time of etching. When the etching is advanced to arrive at an N-type AlGaAs layer 5, its depthwise etching is stopped due to high selection ratio, but sidewisely etching is started. Since the sideetching amount is substantially proportional to its etching time, the photoresists 8, 10 can be formed in an overhanging shape to the layer 6. Thus, source, drain and gate electrodes 11, 6 can be formed by a lift-off method without newly providing a spacer layer for lift-off.

8. 发明专利

JPH01264270A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01264270A
公开(公告)日：1989-10-20
申请号：JP9155588
申请日：1988-04-15
申请人： HITACHI LTD
发明人： TAGAMI TOMONORI , YAMANE MASAO , KOBAYASHI MASAYOSHI , USAGAWA TOSHIYUKI , TAKAHASHI SUSUMU
IPC分类号： H01L29/812 , H01L21/28 , H01L21/338 , H01L29/43 , H01L29/778 , H01L29/80
摘要： PURPOSE:To reduce a resistance without causing a detect in an interface between an electrode extraction layer and a channel by smoothly connecting a conduction band or a valence band in the interface between a source-drain electrode extraction layer and the channel. CONSTITUTION:A high-purity GaAs buffer layer 2 is crystal-grown on a whole face of a substrate 1; a mask 9 is shifted on it; n-type AlGaAs 5 is crystal- grown. Then, n-type GaAs layers 3, 4 are grown; a window is opened only at the upper part of the n-type AlGaAs 5; in etching operation is executed; the active layer 5 is exposed. Then, an AuGe alloy is applied to the drain and source electrode extraction layers 3 and 4 in order to obtain ohmic contact; a metal having the Schottky contact, e.g. Al, is applied to the n-type AlGaAs 5; these are worked individually by using an ordinary photolithographic method and an ordinary lift-off method; a drain electrode 6, a source electrode 7 and a gate electrode 8 are formed. Since the electrode extraction layers and a channel formation layer are deposited continuously, a conduction band or a valence band or both of them are connected smoothly; an increase in a resistance can be eliminated.

9. 发明专利

JPS6360570A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6360570A
公开(公告)日：1988-03-16
申请号：JP20367886
申请日：1986-09-01
申请人： HITACHI LTD
发明人： YAMANE MASAO , KOBAYASHI MASAYOSHI , TAKAHASHI SUSUMU
IPC分类号： H01L29/812 , H01L21/338 , H01L29/778 , H01L29/80
摘要： PURPOSE:To reduce resistance between a source and a gate by forming a hole to an N cap layer, thickness of which is thickened, so that depth is not made larger than the thickness of the cap layer and shaping an ohmic electrode so as to be in contact with the side wall of the hole when forming source drain electrodes. CONSTITUTION:A GaAs layer 2, an AlGaAs layer 3, an N -AlGaAs layer 4, an AlGaAs layer 5 and an N -GaAs layer 6 are grown onto a semi-insulating GaAs substrate 1 in an epitaxial manner in succession. The thickness of the cap layer 6 is thickened at that time. Elements are isolated through mesa etching, an SiO2 film 10 is shaped, a hole is bored by using dry etching, a hole is bored to the layer 6 through wet etching so that depth is not made larger than the thiokness of the layer 6, and SiO2 10 is side-etched, and formed to a shape easy to be lifted off. A source electrode 7 and a drain electrode 8 and clearances 11 are shaped, and a gate electrode 9 is formed. Accordingly, resistance between a source and a gate can be reduced, and breakdown strength can be increased.

10. 发明专利

JPS6314478A MANUFACTURE OF FIELD-EFFECT TRANSISTOR 失效
公开(公告)号：JPS6314478A
公开(公告)日：1988-01-21
申请号：JP15782586
申请日：1986-07-07
申请人： HITACHI LTD
发明人： YANOKURA EIJI , TAKAHASHI SUSUMU , ADAKA SABURO , MORI MITSUHIRO , YAMANE MASAO , MIZUTA HIROSHI
IPC分类号： H01L29/812 , H01L21/28 , H01L21/338 , H01L29/80
摘要： PURPOSE:To make a finely constructed gate electrode offset to the side of a source electrode while forming them in selfaligned manner, by providing an interlayer insulation film composed of two layers, controlling the length of a gate by means of the extent of side etching of the second insulation layer and vapor depositing the gate electrode through an etching window one end of which is defined by the source electrode. CONSTITUTION:An active layer 1 is formed on a semi-insulating GaAs substrate 2. An SiN film 3 as the first insulation layer and an SiO2 film 4 as the second insulation layer are formed thereon. The insulation layers are then etched vertically by the photolithography process in areas where source and drain electrodes are to be formed. Subsequently, the SiO2 film 4 is side etched. Then, a source electrode 7 and a drain electrode 6 are formed by the lift-off process. The substrate is then covered with a photoresist film 8 except an area including the insulation film 3 exposed between the end of the source electrode 7 and the end of the insulation film 4. Said exposed insulation film 3 is selectively etched to form an etching window 10. Subsequently, the active layer 2 is wet etched through the window 10. A gate metal is then vapor deposited and lifted off to provide a gate electrode 9.

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