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1. 发明专利

JPH04369122A D/A CONVERTER 失效
公开(公告)号：JPH04369122A
公开(公告)日：1992-12-21
申请号：JP17167091
申请日：1991-06-17
申请人： HITACHI LTD , HITACHI MICOM SYST KK , HITACHI TOBU SEMICONDUCTOR LTD
发明人： YONETANI HIROYUKI , WATANABE KAZUO , KUROSAWA YUMIO
IPC分类号： H01L21/822 , H01L27/04 , H03M1/74
摘要： PURPOSE:To improve the accuracy of linearity around a zero cross point of a current summing type D/A converter by making a difference between characteristics of two circuit components of the same shape smaller as they are located nearer the center of a semiconductor substrate and shorter in their interval. CONSTITUTION:Constant current circuit elements A1, A2, and A2, A3 are turned on/off respectively depending on a difference of conversion values when a least significant bit of a digital input value changes by one and they are arranged side by side. There appears a property that a difference of characteristics is smaller as the elements An-A1 and B1-Bn arranged in this way are located nearer the center of a semiconductor substrate 10 and their interval is shorter. Thus, without matching by laser trimming, the dispersion in the characteristic of the constant current circuit elements turned on/off around a zero cross point is reduced. Furthermore, the linearity accuracy at a minute change of each conversion value is enhanced.

2. 发明专利

JPH05218840A SIGNAL TRANSMITTING CIRCUIT 失效
公开(公告)号：JPH05218840A
公开(公告)日：1993-08-27
申请号：JP4748792
申请日：1992-02-03
申请人： HITACHI LTD , HITACHI MICOM SYST KK
发明人： YONETANI HIROYUKI , WATANABE KAZUO
IPC分类号： H01L21/8238 , G11C27/02 , H01L27/092 , H03K17/687
摘要： PURPOSE:To provide a signal transmitting circuit which has the excellent transmission characteristic and never produces any undesired distortion of an output waveform despite a large amplitude of the signal to be transmitted in such a case that the signal transmitting circuit consists of a CMOS analog switch. CONSTITUTION:A signal transmitting circuit contains an nMOS transistor TR Qn1 end a pMOS TR Qp2 which are connected in series between the input/ output nodes n1 and n3, a pM0S TR Qp1 and an nMOS TR Qn2 which are connected in series between the nodes n1 and n3 in parallel to the TR Qn1 and Qp2, and a resistance R which has the prescribed resistance value so as to secure a fixed synthetic ON resistance of the signal transmitting circuit and is connected between the connection nodes n21 and n22 of a transistor of each train. In such a constitution, the channel conductance and the threshold voltage are set equal to each other between the TR Qn1, Qn2 and the TR Qp1, Qp2.

3. 发明专利

JPH05227031A INTEGRATION TYPE A/D CONVERSION CIRCUIT 失效
公开(公告)号：JPH05227031A
公开(公告)日：1993-09-03
申请号：JP5669692
申请日：1992-02-08
申请人： HITACHI LTD , HITACHI MICOM SYST KK
发明人： YONETANI HIROYUKI , WATANABE KAZUO
IPC分类号： H03M1/20 , H03M1/52
摘要： PURPOSE:To accurately set up a proper dither quantity by means of simple timing control by providing the integration type A/D conversion circuit with a dither current source set up with a prescribed ratio to the current value of an integration constant current source and controlling a dither injection quantity in accordance with the injection time of a dither current. CONSTITUTION:During the low level period of a control signal SH, an analog input voltage AV is fetched in to a capacitor C1. When the signal SH is changed to a high level and a switch SW1 is switched to an off state, a reset pulse RP is generated and a counter circuit CNT is reset. When the pulse RP is turned to a low level, a switch SW2 is turned on and integrating operation based on a constant current Io and the discharge of a capacitor C1 are started. At the time, a dither pulse DTH is generated, a switch SW3 is turned on and a dither current Id is added to an integration current. When the output voltage of an operational amplifier A1 reaches a reference voltage VR2, an AND gate circuit G1 is closed and counting is stopped.

4. 发明专利

JP2000040964A COMPARISON CIRCUIT AND A/D CONVERSION CIRCUIT 失效
公开(公告)号：JP2000040964A
公开(公告)日：2000-02-08
申请号：JP20878298
申请日：1998-07-24
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： HABUKA TOSHITO , YONETANI HIROYUKI
IPC分类号： H03M1/08 , H03M1/38 , H03M1/46
摘要： PROBLEM TO BE SOLVED: To provide the comparing circuit with low power consumption and low noise and further to reduce the power consumption and noise of a sequential comparison type AD converting circuit, including the comparing circuit using a CMOS inverter type amplifier circuit by preventing the through-current of the comparing circuit. SOLUTION: This comparison circuit CMP consists of a CMOS inverter type amplifier circuit AMP, a 1st switch means SW2 connected between the input and output terminals of the amplifier circuit, a sampling capacitor Cs connected between the input terminal of the amplifier circuit and an analog input terminal, and a changeover switch means SW1 which can supply the voltage at the analog input terminal or comparison voltage selectively to one terminal of the sampling capacitor; and 2nd switch means MP4 and MN4 are connected in series with the MOSFET constituting the amplifier circuit and turned on only in a sampling period of analog input to the sampling capacitor and a stable period of input to the amplifier circuit to perform amplifier operation.

5. 发明专利

JPH098619A INPUT SELECTION CIRCUIT 失效
公开(公告)号：JPH098619A
公开(公告)日：1997-01-10
申请号：JP15194195
申请日：1995-06-19
申请人： HITACHI LTD , HITACHI MICROCOMPUTER SYST
发明人： YONETANI HIROYUKI , KAWAMOTO MIKIHIKO , MATSUDA KATSUHISA
IPC分类号： G01R31/28 , H03K17/00 , H03K17/62
摘要： PURPOSE: To efficiently perform a noise test required for product evaluation in a short period by providing plural input ports, plural analog input circuits, output port, alternative selection control circuit and simultaneous selection control circuit. CONSTITUTION: Based on a first control signal Vcnt , an alternative selection control circuit 5 selectively operates only one of two analog input circuits 21 and 22. Based on a second control signal Vref , a simultaneous selection control circuit 6 simultaneously operates two circuits 21 and 22. The total sum of noises generated at the respective circuits 21 and 22 are led out to an output port 4 by the circuits 5 and 6. By measuring the total sum of noises appearing at the port 4, it can be decided whether the noise higher than an allowable level is generated or not at the input circuit 21 or 22 at least. Thus, the test suitability of an input selecting circuit for plural input circuits can be improved.

6. 发明专利

JP2003008432A Pll use filter circuit and pll circuit 审中-公开
标题翻译： PLL使用滤波电路和PLL电路
公开(公告)号：JP2003008432A
公开(公告)日：2003-01-10
申请号：JP2001194190
申请日：2001-06-27
申请人： Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： YONETANI HIROYUKI , HOTTA RYUTARO , NAKANO KENICHI
IPC分类号： H03L7/093
摘要： PROBLEM TO BE SOLVED: To stably conduct a loop control without needing a large layout area in an LSI and impairing the latitude of layout design so much and to reduce the phase noise of a VCO(voltage control oscillator) by enhancing noise immunity in a PLL use filter circuit that applies filtering processing to a pulsive phase difference detection signal outputted by a switching operation of a charge pump circuit to obtain a frequency control signal for a variable frequency oscillator. SOLUTION: A plurality of filter circuits stepwise provide a frequency characteristic to the filtering processing and the 1st filter circuit 41 first receiving an output of the charge pump circuit 3 comprises a capacitive element C3 connected in parallel with the output of the charge pump circuit 3.
摘要翻译：要解决的问题：为了稳定地进行环路控制而不需要在LSI中的大的布局面积，并且大大削弱了布局设计的宽容度，并且通过增强PLL中的抗噪声性能来降低VCO（压控振荡器）的相位噪声使用滤波电路，对电荷泵电路的开关动作输出的脉动相位差检测信号进行滤波处理，得到变频振荡器的频率控制信号。解决方案：多个滤波器电路逐步提供滤波处理的频率特性，第一滤波电路41首先接收电荷泵电路3的输出包括与电荷泵电路3的输出并联连接的电容元件C3。

7. 发明专利

JPS6454813A CONTROL CIRCUIT 失效
公开(公告)号：JPS6454813A
公开(公告)日：1989-03-02
申请号：JP21012687
申请日：1987-08-26
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： YONETANI HIROYUKI , WATANABE KAZUO
IPC分类号： H03F1/02 , H03K17/687 , H03K17/693 , H03K19/00
摘要： PURPOSE:To reduce power consumption in a constant current circuit, by providing a CMOS inverter which generates and cuts constant voltage output corresponding to a control signal and a MOSFET switching element which actuates the constant voltage output as bias voltages and forms the constant current circuit. CONSTITUTION:A control circuit 1 is constituted of a CMOS inverter A and a MOSFETM3 that is a switching element. When the control signal I supplied to a terminal T1 is set at a low level, a P-channel MOSFETM1 is turned on, and an output load capacitor CL is charged. The bias voltage VB appears at a terminal T2, and the M3 passes a constant current I0 between the drain and the source, and at this time, no current flows on the gate G. Meanwhile, when the control signal is set at a high level, the M1 is turned off, and the M2 is turned on, and the output load capacitor CL is discharged, then, inverter output at the terminal T2 goes to a GND level, and the M3 is turned off, then, a current path between the drain and the source is cut off, consequently, the constant current I0 is also cut off. In such a way, it is possible low power consumption and the constant current.

8. 发明专利

JP2001210020A RECORDED INFORMATION REPRODUCING DEVICE 失效
公开(公告)号：JP2001210020A
公开(公告)日：2001-08-03
申请号：JP2000023261
申请日：2000-01-27
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： JINBO HIRONORI , YONETANI HIROYUKI
IPC分类号： G11B20/10 , G11B7/005 , G11B20/14 , H03L7/07 , H03L7/08 , H03L7/081 , H03L7/099 , H04L7/02 , H04L7/033
摘要： PROBLEM TO BE SOLVED: To provide a recorded information reproducing device reducing an error occurring when a synchronizing clock signal is generated from a signal read from a recording medium and the data are reproduced, and reproducing the high quality digital data. SOLUTION: A data reproducing means 12 uses a binarized signal 11 as a reference signal, and generates a reproducing clock signal 14 in a PLL circuit 21. The voltage control oscillator 32 of the PLL circuit outputs n lines of clock signals 23 whose phases are shifted nearly, uniformly and respectively 2 π/n each together with the reproducing clock signal. A delay control circuit 26 outputs a delay control signal changing a conversion point of a delay signal in the direction away from the rise timing of the reproducing clock signal to a variable delay circuit based on the phase relations between the delay signal 24 delaying the binarized signal with the variable delay circuit 22 and n lines of clock signals.

9. 发明专利

JPH10241105A REPRODUCTION EQUALIZER CIRCUIT 失效
公开(公告)号：JPH10241105A
公开(公告)日：1998-09-11
申请号：JP5554697
申请日：1997-02-24
申请人： HITACHI LTD , HITACHI CHIYOU LSI SYS KK
发明人： YONETANI HIROYUKI , WATANUKI YUJI , KAWAMOTO MIKIHIKO
IPC分类号： G11B5/027 , G11B5/035 , H03G5/02
摘要： PROBLEM TO BE SOLVED: To provide a reproduction equalizer circuit realizing a simplified circuit while suppressing noise occurrence upon switching. SOLUTION: With respect to a negative feedback loop of a first operational amplifying circuit 2 which receives an audio reproduction signal from a magnetic head 1 for reproduction and recording, a capacitance duplicate circuit 4 is provided to include a first capacitor C1 and a second operational amplifying circuit 6 and equivalently double a capacitance value of the first capacitor C1. A second capacitor C2 and a switching element SW are further provided between an output node of the first capacitor C1 constituting the capacitance duplicate circuit 4 and an AC ground point. When the switching element SW is in an OFF state, an NAB characteristic c orresponding to a high position tape is set by the first capacitor C1 and the capacitance duplicate circuit 4. When the switching element SW is in an ON state, another NAB characteristic corresponding to a normal position tape is set by allowing a high frequency feedback amount to pass by the second capacitor C2.

10. 发明专利

JPH0227401A OFFSETTING CONTROL CIRCUIT 失效
公开(公告)号：JPH0227401A
公开(公告)日：1990-01-30
申请号：JP17681488
申请日：1988-07-15
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： YONETANI HIROYUKI , WATANABE KAZUO
IPC分类号： G05B1/02 , H03F3/34 , H03F3/347
摘要： PURPOSE:To automatically correct the offsetting of a comparator, a differential amplifier circuit and the like without using an external terminal in an LSI internal part by correcting the input level of a controlled circuit by the correcting level set automatically so as to make the offsetting of the controlled circuit into zero. CONSTITUTION:When an initializing signal Is is set to H level, the comparing input of a comparator 1 which is a controlled circuit and the reference input are mutually shorted to the same potential and a comparing output Co is switched to the detecting input side of an output change detecting circuit 3. When a resetting signal Rs is given, an output level I of a variable level generating circuit 4 is continuously changed and added to the reference input level of a comparator 1 by a level control circuit 5. When the input level passes through a point which becomes an offsetting zero, the output change detecting circuit 3 switches a detecting output Do from H level to L level simultaneously when the comparing output Co is changed and stops the stepping action of a counter 41. Thus, the input offset of the comparator 1 is automatically corrected.

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