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1. 发明专利

JP2001244291A WIRE BONDING EQUIPMENT 失效
公开(公告)号：JP2001244291A
公开(公告)日：2001-09-07
申请号：JP2000052044
申请日：2000-02-28
申请人： HITACHI LTD , HITACHI HARAMACHI SEMI CONDUCT
发明人： SATO AKIRA , ONARI JUNICHI , TAKAYANAGI YUJI , SHINNO YUJI
IPC分类号： H01L21/60
摘要： PROBLEM TO BE SOLVED: To reduce stress applied on a semiconductor element or inner leads when forming and pressure-connecting a bonding wire. SOLUTION: In wire bonding equipment, the bonding wire 6 guided by a wire guide 8 is connected to a semiconductor element 4 or inner lead on a lead frame 1 using a bonding tool 7. The bonding wire has a cross section formed into a non-circular shape, and then is pressure-connected to the semiconductor element or inner lead by the bonding tool. Between the wire guide and a part of the wire to be pressure-connected by the bonding tool, a wire forming tool is installed to form the bonding wire. The wire forming tool consists of a projecting part of the bonding tool and a flat part of the wire guide.

2. 发明专利

JPH04299835A SEMICONDUCTOR DEVICE AND MANUFACTURE 失效
公开(公告)号：JPH04299835A
公开(公告)日：1992-10-23
申请号：JP6498191
申请日：1991-03-28
申请人： HITACHI LTD , HITACHI HARAMACHI SEMI CONDUCT
发明人： NAKANO YASUKI , MORI MUTSUHIRO , KUROSU TOSHIKI , SHINNO YUJI , IWABUCHI KATSUHIRO , KURITA SHINICHI
IPC分类号： H01L29/78 , H01L21/336
摘要： PURPOSE:To provide a semiconductor device and a manufacturing method which prevent the short circuit between a gate electrode and a source electrode. CONSTITUTION:An n layer 12 is formed on a semiconductor substrate 11 having a drain electrode 41; insulating gates composed of three layers by a gate oxide film 21, a gate electrode 31 and an insulating film 22 are formed at equal intervals on the n layer 12. P-type impurities, e.g. boron, are ion-implanted by making use of the insulating gates as a mask; a P-layer 13 is formed. An insulating film 24 which contains impurities is filled into a region in which both ends of the gate electrode 31 are retreated respectively to the inside from the end of the insulating film 22; it covers the whole side faces of both end parts of the insulating gates; it is used to insulate the gate electrode 31 from a source electrode 42. Impurities, e.g. phosphorus, in the insulating film 24 are diffused into the P-layer 13 from the film; an n layer 15 is formed. The source electrode 42 comes into contact with the diffusion region in the transverse direction of the n layer 14 and with the P-layer 13.

3. 发明专利

JPH0867995A PLASMA ETCHING DEVICE 失效
公开(公告)号：JPH0867995A
公开(公告)日：1996-03-12
申请号：JP20329994
申请日：1994-08-29
申请人： HITACHI LTD , HITACHI HARAMACHI SEMI CONDUCT
发明人： TAKAHASHI KAZUYUKI , HAYASHI SHOJI , SHINNO YUJI , SAKANIWA HIROTAKA
IPC分类号： C23F4/00 , H01L21/302 , H01L21/3065
摘要： PURPOSE: To increase the number of produced nondefective semiconductor devices and to improve reliability by uniformizing the etching rate in the etching surface of a material to be etched. CONSTITUTION: A material 12 to be etched is placed on a lower electrode (stage) 11, a chamber 1 is evacuated from an exhaust port 5 to a specified vacuum, and a reacting gas variable with the kind of the material 12 is introduced from an inlet 6. A high-frequency electric field is impressed on an upper electrode 10, the upper electrode 10 or the lower electrode is rotated at a specified speed, and the material 12 is etched in a plasma state.

4. 发明专利

JP2001044414A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2001044414A
公开(公告)日：2001-02-16
申请号：JP22140099
申请日：1999-08-04
申请人： HITACHI LTD , HITACHI HARAMACHI SEMI CONDUCT
发明人： TAKAYANAGI YUJI , ONARI JUNICHI , SAKURABA KOJI , TAKAHASHI KAZUYUKI , SHINNO YUJI
IPC分类号： H01L29/06 , H01L21/28 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To form a gate structure suitable for a pressure contact semiconductor device with less proportion of termination region to a chip area by constituting at least a second electrode of a barrier metal layer. SOLUTION: A p-n-p type transistor is constituted of a p-type emitter layer 11, a n-type semiconductor substrate 1, and a p-type collector layer 21, and an insulating gate transistor which controls the p-n-p type transistor is constituted of a gate electrode 13, a n-type layer 12, the p-type emitter layer 11, and the n-type semiconductor substrate 1. A barrier metal layer 43 is in ohmic contact with a guard ring 41 via contact hole 201, and the barrier metal layer 43 expands a depletion layer formed on the n-type semiconductor substrate with a field oxide film 42 in-between, and thereby relaxes the electric field concentration. Therefore, a semiconductor device of gate structure, which is less in proportion of the termination region to a chip area and is suitable for cold-welded semiconductor devices, can be obtained.

5. 发明专利

JPH11121611A MANUFACTURE OF DIELECTRIC SEPARATION SUBSTRATE 失效
公开(公告)号：JPH11121611A
公开(公告)日：1999-04-30
申请号：JP28485097
申请日：1997-10-17
申请人： HITACHI LTD , HITACHI HARAMACHI SEMI CONDUCT
发明人： SAKURABA KOJI , HORIUCHI JUNICHIRO , SHINNO YUJI , KURITA SHINICHI , KUMAHARA KENJI
IPC分类号： H01L21/762 , H01L21/02 , H01L21/76 , H01L27/12
摘要： PROBLEM TO BE SOLVED: To reduce a size and a change of a bent amount if a species of products is differed, by a method wherein a thickness of a monocrystal semiconductor substrate to be a support body is regulated in responce to a thickness of a monocrystal island region. SOLUTION: A separation groove 2 is formed on one face of a monocrystal silicon substrate 1, and silicon oxide films 3 4 are formed on both faces of the monocrystal silicon substrate 1 by thermal oxidation, and a polycrystal silicon layer 5 is deposited on the silicon oxide film 3 on a formation face of the separation groove 2, and the surface is smoothed by grinding and polishing, so that a thickness t2 is regulated to be 10 to 50 μm. A monocrystal silicon substrate 9 to be a support body is adhered to the surface and the substrate 1 is ground and polished, the so-formed space between a monocrystal island region 7 of a thickness t7 and the polycrystal silicon layer 5 is insulated by the silicon oxide film 3, and a thickness t4 of a silicon substrate 9 is also regulated in response to the thickness t3 of the island region 7. Accordingly, if a species of products is differed, it is possible to reduce a size and a change of a bent amount of a dielectric separation substrate.

6. 发明专利

JPH06275604A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH06275604A
公开(公告)日：1994-09-30
申请号：JP6031593
申请日：1993-03-19
申请人： HITACHI LTD , HITACHI HARAMACHI SEMI CONDUCT
发明人： KIKUCHI MASAHIRO , KURITA SHINICHI , SHIMURA TATSUO , TAKITA JUNICHI , SHINNO YUJI
IPC分类号： H01L21/3205 , H01L21/28 , H01L21/31 , H01L21/314 , H01L23/52
摘要： PURPOSE:To provide a highly reliable semiconductor device in which cracks appearing in a final passivation film are fundamentally prevented. CONSTITUTION:A semiconductor device is a device where an expression, A>=0.01(mum )X-BXC holds when the thickness of a final passivation film 3 is expressed as A, the sum of the thickness of the film of the electrode wiring 4 of, at least, one layer, is expressed as B, and the width of a line of the electrode wiring 4 is expressed as C in a semiconductor device. Thus, when the final film is thickened to maintain this relationship, the stress exerted on this film itself will be small, and the stress is dispersed to make the localized concentration small, thereby preventing the influence of the stress exerted from a mold material to the electrode wiring without any cracks caused in the final passivation film.

7. 发明专利

JPH0653102A DIELECTRIC ISOLATED SUBSTRATE 失效
公开(公告)号：JPH0653102A
公开(公告)日：1994-02-25
申请号：JP20657492
申请日：1992-08-03
申请人： HITACHI LTD , HITACHI HARAMACHI SEMI CONDUCT
发明人： OWADA NOBUHITO , KURITA SHINICHI , KINASHI MASAKI , URUNO TOSHIO , SHIMURA TATSUO , SHINNO YUJI
IPC分类号： H01L21/02 , H01L21/76 , H01L21/762 , H01L27/12
摘要： PURPOSE:To prevent a substrate itself from bending after formation of a silicon thermal oxide film by setting the ratio of B to A so that an absolute value of a radius of curvature of the dielectric isolated substrate which has been through a high temperature treatment process may be a specified value or above, where A is the thickness of a polycrystalline silicon supporter layer and B is the thickness of a multilayer supporter layer. CONSTITUTION:The thickness of a polycrystalline silicon supporter layer 5 is A and the thickness of a multilayer supporter layer which is manufactured by laminating silicon oxide films 6 and polycrystalline silicon thin layers 7 is B. When the thickness of a silicon thermal oxide film 14 is 1.5-3.5mum and the ratio of B to A is 1-5 or when the thickness of the silicon thermal oxide film 14 is 1.3-3.7mum and the ratio of B to A is 1.5-4.5, a good region is attained where an absolute value of a radius of curvature is 40m or above and there is no bow. When the silicon thermal oxide film 14 is 1.5-3.5mum in thickness and the ratio of B to A is 2-4, the best region is attained where an absolute value of a radius of curvature is 100m or above and a bow hardly appears.

8. 发明专利

JPH03105945A MANUFACTURE OF DIELECTRIC INSULATION AND ISOLATION SUBSTRATE 失效
公开(公告)号：JPH03105945A
公开(公告)日：1991-05-02
申请号：JP24219389
申请日：1989-09-20
申请人： HITACHI LTD
发明人： SHINNO YUJI
IPC分类号： H01L21/762 , H01L21/76
摘要： PURPOSE:To enhance an isolation yield of a dielectric isolation substrate by a method wherein, after a V-shaped groove has been formed, a U-shaped groove in a vertical direction is formed at a tip part of the V-shaped groove and the trench is filled with a thermal oxide film in a thermal oxidation process after that. CONSTITUTION:An opening part 13 is formed in a prescribed region of an SiO2 film 12 by a photolithographic technique. Then, an Si single-crystal substrate 11 is etched anisotropically to form a V-shaped groove 14. An Si nitride film 15 is formed by a low-pressure CVD method; a polyimide-based resin 16 is coated in such a way that the V-shaped groove 14 is filled; an opening part 17 is formed at a tip part of the V-shaped groove 14. In addition, a trench 18 is formed by an anisotropic dry etching operation. Then, impurities of arsenic, antimony or the like are diffused to the whole surface to form an n type buried layer 19. Then, an SiO2 film 12' is formed by a thermal oxidation method. The trench 18 is filled with the SiO2 film 12' by the oxidation.

9. 发明专利

JP2004241737A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2004241737A
公开(公告)日：2004-08-26
申请号：JP2003031962
申请日：2003-02-10
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： WAKIZAWA YUUJI , TABATA TOSHIHITO , MATSUURA KATSUYA , SHINNO YUJI , TAKAYANAGI YUJI , SATO MASAO
IPC分类号： H01L21/762 , H01L21/02 , H01L27/12
摘要： PROBLEM TO BE SOLVED: To relax bending after a rear surface is ground, in a semiconductor device provided with a dielectric isolated substrate.
SOLUTION: A supporting substrate is provided with an insulation film in a specified position therein, and it is ground so that the insulation film of the supporting substrate may be left in the rear surface grinding step of a final manufacturing step, thereby relaxing bending after the rear surface is ground. Thus, cracks in a passivation film or vacuum suction failure during transfer of wafers can be prevented.
COPYRIGHT: (C)2004,JPO&NCIPI

10. 发明专利

JPH08222625A MANUFACTURE OF DIELECTRIC ISOLATION BOARD 失效
公开(公告)号：JPH08222625A
公开(公告)日：1996-08-30
申请号：JP2148495
申请日：1995-02-09
申请人： HITACHI LTD
发明人： SAKURABA KOJI , HAYASHI SHOJI , SHINNO YUJI , SAKANIWA HIROTAKA
IPC分类号： H01L21/762 , H01L21/02 , H01L27/12
摘要： PURPOSE: To eliminate a bent of a substrate at the time of heat treating at a high temperature by forming an insulating film on a single crystalline silicon substrate having grooves, then removing the film of the part which is not used as an integrated circuit, and simultaneously depositing a single crystalline silicon layer together with a polycrystalline silicon layer on the other part. CONSTITUTION: Insulating films 3, 4 are formed on a single crystalline silicon substrate 1 having grooves 2 on one main surface, and a polycrystalline silicon 6 is deposited on the main surface having the grooves 2 by a vapor growing method. Then, the surface of the silicon layer 6 is ground and polished to be flattened mirror surface, and a dielectric isolation substrate 13 is manufactured via the step of laminating the mirror surface and the main surface of a single crystalline silicon substrate 10. In this case, the film 3 of the part 5 which is not used as an integrated circuit on the main surface having the grooves 3 is removed, and a single crystalline silicon 7 is deposited at the part simultaneously by a vapor growing method to prevent the vent of the substrate 13. For example, the insulating film removed part of the part 5 which is not used as the integrated circuit is arranged on the entirety of the substrate.

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