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1. 发明专利

JPH0918328A VOLTAGE LEVEL SHIFTING CIRCUIT 失效
公开(公告)号：JPH0918328A
公开(公告)日：1997-01-17
申请号：JP16513095
申请日：1995-06-30
申请人： HITACHI LTD , HITACHI HARAMACHI SEMI CONDUCT
发明人： SUZUKI RYOICHI , OURA HITOSHI , KAWAMOTO KOJI
IPC分类号： H03K19/0185
摘要： PURPOSE: To provide the level shifting circuit of low power consumption usable at a voltage higher than a pMOSFET gate withstand voltage. CONSTITUTION: MOSFETs Q5 and Q6 are made into high voltage nMOSFETs for which a current value is limited so as not to make the gate potential of a pMOSFET lower than the withstand voltage. When Vin is an 'H' level, the MOSFET Q5 is 'ON' and an output terminal N5 becomes an 'L' level, however, since the current value is limited, the voltage is applied to the nMOSFET and the gate potential of the MOSFETs Q1 and Q2 does not become lower than the withstand voltage. Since the high voltage MOSFET for which the current value is limited so as not to make the gate potential of the pMOSFET lower than the withstand voltage is used, this circuit can be used even by the voltage higher than the pMOSFET gate withstand voltage.

2. 发明专利

JPH08237096A DRIVE CIRCUIT FOR CAPACITIVE LOAD 失效
公开(公告)号：JPH08237096A
公开(公告)日：1996-09-13
申请号：JP3969095
申请日：1995-02-28
申请人： HITACHI LTD , HITACHI HARAMACHI SEMI CONDUCT
发明人： OURA HITOSHI , KAWAMOTO KOJI , OZEKI SHOICHI
IPC分类号： H03K17/04 , H03K17/06 , H03K17/56
摘要： PURPOSE: To realize a drive circuit for a capacitive load in which a sharp output waveform is obtained regardless of simple circuit configuration. CONSTITUTION: In the circuit configuration where a diode 4 is provided between an emitter of an upper side IGBT(insulated gate bipolar transistor) 3 and a gate of the upper element is connected to a collector of the lower element, another IGBT 9 is provided to the lower side and a collector of the IGBT 9 connects to the emitter of the upper side IGBT 3. Through the constitution above, since a reverse recovery current of the diode 4 is suppressed, a sharp output waveform is obtained regardless of the simple circuit configuration.

3. 发明专利

JPH08167712A SEMICONDUCTOR DEVICE AND IC 失效
公开(公告)号：JPH08167712A
公开(公告)日：1996-06-25
申请号：JP31020294
申请日：1994-12-14
申请人： HITACHI LTD , HITACHI HARAMACHI SEMI CONDUCT
发明人： OZEKI SHOICHI , SUDA KOICHI , OURA HITOSHI , KAWAMOTO KOJI
IPC分类号： H01L29/78 , H01L21/336 , H01L29/739
摘要： PURPOSE: To reduce the fall time of an IGBT included in an IC by ordinary IC technology without irradiation with an electron beam by extracting a second conductivity type semiconductor layer including a collector region formed of a first conductivity type semiconductor layer as an electrode. CONSTITUTION: A heavily doped control collector layer 4 is provided on an N-type substrate 1, and brought into ohmic contact with an output electrode 4b. The potential of a second conductivity type semiconductor layer including the layer 4 made of a first conductivity type semiconductor is output as an electrode, and a circuit for short-circuiting a collector electrode 3a to a control electrode at the time of OFF of a lateral IGBT is added in an IC including the IGBT. Thus, carrier flowing to a MOS is fed from the layer 4 to the control collector electrode via the second layer and the electrode 3a via short-circuiting. Thus, at the time of OFF of the IGBT, the injection of excess carriers from the first layer to the second layer is eliminated, and hence a fall time can be shortened.

4. 发明专利

JPH07335744A MANUFACTURE OF DIELECTRIC ISOLATING SUBSTRATE 失效
公开(公告)号：JPH07335744A
公开(公告)日：1995-12-22
申请号：JP12348094
申请日：1994-06-06
申请人： HITACHI LTD , HITACHI HARAMACHI SEMI CONDUCT
发明人： OWADA NOBUHITO , KURITA SHINICHI , SAKAGAMI TAKESHI , KAWAMOTO KOJI , SAKURABA KOJI
IPC分类号： H01L21/762 , H01L21/02 , H01L27/12
摘要： PURPOSE:To prevent the defective joining of joint surfaces by thermally treating a laminated wafer in the direct joining of polycrystalline silicon and single crystal silicon within a specific temperature range as the heat treatment of the wafer. CONSTITUTION:In the heat treatment process of a wafer after laminating during the direct joining process of the wafer, the temperature of heat treatment correlates with the generation of voids. Consequently, it is considered that the temperature of heat treatment correlates with the generation of the voids even in the direct joining of polycrystalline silicon and single crystal silicon, and the generation of the voids to the temperature of heat treatment is examined. The result of the examination is shown in a graph. The axis of abscissas in the graph represents the temperature of heat treatment after laminating and the axis of ordinates the fraction defective of the joining of joint surfaces. The fraction defective of joining is reduced with a temperature rise, and a region, in which no defective joining is generated, is obtained within the range of a temperature of 1150-1250 deg.C. When the temperature is elevated to 1250 deg.C or higher, the fraction defective of joining is augmented again. Accordingly, the temperature of heat treatment after laminating is optimized, thus hardly generating defective joining.

5. 发明专利

JPS63249333A MANUFACTURE OF POWER IC 失效
公开(公告)号：JPS63249333A
公开(公告)日：1988-10-17
申请号：JP8299287
申请日：1987-04-06
申请人： HITACHI LTD , HITACHI HARAMACHI SEMI CONDUCT
发明人： KAWAMOTO KOJI , KURITA SHINICHI
IPC分类号： H01L21/28 , H01L21/76 , H01L21/762 , H01L29/41
摘要： PURPOSE:To obtain a high-performance power IC which is highly integrated and small-sized enough to decrease reactive power loss substantially and still provides high reliability, by forming a substrate contact region by means of selective oxidation performed during formation of a field oxide film instead of etching the oxide film. CONSTITUTION:After a thin oxide film 7' is formed on the surface of an element, an anti-oxidant Si3N4 film 10 is formed on a part of the surface where a substrate contact region is to be provided. A field oxide film 6 is then formed by thermal oxidation and the Si3N4 film 10 is removed thereafter. The thick field oxide film 6 thus formed is connected to the thin oxide film 7' in the substrate contact region with gently inclined junctions. Accordingly, there is no need of etching the oxide film. Even if the element isolating oxide film is overlapped with the substrate contact region, the element isolating oxide film can be reserved as it is. Thus, it is possible to obtain a high-performance power IC which is highly integrated and small-sized enough to decrease reactive power loss substantially, and still provides high reliability.

6. 发明专利

JPH11313488A DRIVE CIRCUIT FOR INVERTER DEVICE 失效
公开(公告)号：JPH11313488A
公开(公告)日：1999-11-09
申请号：JP11816298
申请日：1998-04-28
申请人： HITACHI LTD , HITACHI HARAMACHI SEMI CONDUCT
发明人： OURA HITOSHI , KAWAMOTO KOJI
IPC分类号： H02M7/5387
摘要： PROBLEM TO BE SOLVED: To reduce power consumption when integrating a circuit by using a level shift circuit being operated by a pulse signal, and by keeping on an upper-arm switching element by the retention function of drive charge, only during a pulse period. SOLUTION: A lower arm QB1 is turned on and off by a control signal SB, via a driving circuit 3 where VCC is used as a power supply. An upper arm QT1 is driven by a drive element M5, where a power supply VCH for the upper arm is used as the power supply. An upper arm ST gives an external signal from a circuit 11 for driving switching elements S1 and S2 by a signal with the same logic as an upper-arm switching element to have it operate. When the element S1 is turned on and voltage drops in a resistor Ra for lowering potential, the signal is transferred by logic inverters 8 and 9, and a P- channel switching element M5 is turned on for driving the QT1. After the drive period of QT1, the P-channel switching element M5 is turned off, and if the QT1 that is a voltage-type switching element is once driven, a driving voltage is kept and on-state is maintained, since the QT1 is a voltage-type switching element.

7. 发明专利

JPH1026952A CAPACITIVE LOAD DRIVE CIRCUIT AND DISPLAY DEVICE 失效
公开(公告)号：JPH1026952A
公开(公告)日：1998-01-27
申请号：JP18187096
申请日：1996-07-11
申请人： HITACHI LTD , HITACHI HARAMACHI SEMI CONDUCT
发明人： SHIINA KAZUHIRO , KAWAMOTO KOJI , MIURA MASAHITO , OURA HITOSHI , OZEKI SHOICHI
IPC分类号： G09G3/20 , H03K17/56
摘要： PROBLEM TO BE SOLVED: To reduce power consumption by cutting a current flowing through gate resistance of an upper side insulation gate bipolar transistor (IGBT) by a switch in a period when plural outputs become low. SOLUTION: PMOS transistors QP1-QPn are connected between gate terminals and collector terminals of the upper side IGBT QT1-IGBT QTn of totem-pole connected IGBTs, and the gate terminals of respective PMOS transistors QP1-QPn are controlled by a common drive circuit. At a scan drive time, by applying a fixed voltage to the gate electrodes of the PMOS transistors QP1-QPn, the currents are made a constant current, and the currents flowing through lower side IGBTs Q1-Qn are limited. In the period performing the drive that all outputs Q1-On become low, the current flowing through the lower side IGBTs Q1-Qn is cut by making the gate electrodes of the PMOSs QP1-QPn a threshold value voltage or below. Thus, the current consumed in all low period when plural channels are constituted is made nearly zero.

8. 发明专利

JPH0888550A SEMICONDUCTOR CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH0888550A
公开(公告)日：1996-04-02
申请号：JP22475394
申请日：1994-09-20
申请人： HITACHI LTD , HITACHI HARAMACHI SEMI CONDUCT
发明人： OURA HITOSHI , KAWAMOTO KOJI , OZEKI SHOICHI
IPC分类号： H02M7/537 , H02M1/08 , H03K17/00 , H03K17/082 , H03K17/16 , H03K17/56
摘要： PURPOSE: To reduce power consumption and to reduce a chip area by connecting a capacitor between the gate of the MOSFET for gate shortcircuit of a bipolar transistor and the collector of the bipolar transistor. CONSTITUTION: When a transiently changing voltage is applied between the collector and the emitter, a displacement current flows between fixed potential V0 and the emitter electrode of an insulating gate bipolar transistor(IGBT) 1 via the capacitor 3 and the gate and source electrodes of the MOSFET 2 for gate short-circuit. The gate parasitic capacitances 8, 9 of the FET 2 are charged by the displacement current, which connects electrically the drain electrode to the source electrode. While, the parasitic capacitances 6, 7 of the IGBT are also charged. An electric charge which charges the parasitic capacitances is discharged via the FET 2. Therefore, the gate voltage of the IGBT is not increased, which excludes to turn, on the IGBT, and the displacement current flows only when the voltage changes. which reduces the power consumption.

9. 发明专利

JPH09172366A LEVEL SHIFT CIRCUIT AND INVERTER USING THE CIRCUIT 失效
公开(公告)号：JPH09172366A
公开(公告)日：1997-06-30
申请号：JP33150195
申请日：1995-12-20
申请人： HITACHI LTD , HITACHI HARAMACHI SEMI CONDUCT
发明人： OURA HITOSHI , SUDA KOICHI , KAWAMOTO KOJI , MIURA MASAHITO
IPC分类号： H03K5/02 , H03K19/0185 , H03K19/0948 , H03K19/20
摘要： PROBLEM TO BE SOLVED: To prevent malfunction of an arm power switching element by turning off other switching elements when one switching element is turned on. SOLUTION: A dV/dt in a floating potential VM is not generated before an arm power switching element QT1 does not start turning on with an on- signal pulse from a low voltage circuit delivered to an upper arm. A resistance Ra of an off-side pulse transmission system of a level shift circuit 1 is reduced in this case by a means of the other side to reduce the resistance. Thus, a voltage drop by a resistor Rb in the on-side pulse transmission system is not caused on the occurrence of the dV/dt. Even when the occurrence of the dV/dt continues without the on-signal pulse, the signal from the off-side pulse transmission system cannot reach a flip-flop 4 by a holding function of the 'means of the other side to reduce the resistance'. Thus, even on the occurrence of the dV/dt due to self-excitation, no effect is imposed on the upper arm power switching element QT1.

10. 发明专利

JPS63311744A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS63311744A
公开(公告)日：1988-12-20
申请号：JP14706287
申请日：1987-06-15
申请人： HITACHI LTD , HITACHI HARAMACHI SEMI CONDUCT , HITACHI ENG CO LTD
发明人： KARIYA TADAAKI , KAWAMOTO KOJI , KURITA SHINICHI , YUZAWA NOBORU , OKUTSU MITSUHIKO
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/8238 , H01L27/08 , H01L27/092 , H01L29/78
摘要： PURPOSE:To protect a low tension controlling circuit from an electric field and ensure a stable operation by a method wherein coverage is provided by electrodes only on the upper surface of an isolating region in the low tension controlling circuit. CONSTITUTION:Isolating regions I-III are respectively covered by electrodes 52 and, being of a low tension controlling circuit, are of the ground potential, low tension source potential, or of a potential somewhere between the two. Under such conditions, the Al electrodes 52 serve as shields against the outer electric field. Through the intermediary of an interlayer passivation film 53 of the isolating region II, an Al electrode 54 is formed. The Al electrode 54 is set at the ground potential, low tension controlling circuit power source potential, or at a potential somewhere between the two, and serves as a shield against the outer electric field. In the other cross sections of the isolating regions I-III, the Al electrodes 52 do not provide a complete coverage. At locations free of the Al electrodes 52, an Al electrode 54 is formed again to serve as a shield. In this way, a low tension controlling circuit chip surface is rendered completely free of adverse effects of an electric field to be formed by a high tension circuit in an IC of high breakdown strength.

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