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1. 发明专利

JPH11127070A SEMICONDUCTOR CIRCUIT 失效
公开(公告)号：JPH11127070A
公开(公告)日：1999-05-11
申请号：JP29071697
申请日：1997-10-23
申请人： HITACHI LTD , HITACHI DEVICE ENG , HITACHI ULSI SYS CO LTD
发明人： NANBU HIROAKI , HONMA NORIYUKI , KANETANI KAZUO , YAMAZAKI SU , OHATA KENICHI , ARAKAWA FUMIHIKO , KUSUNOKI TAKESHI , HIGETA KEIICHI , NISHIYAMA MASAHIKO , YAMAGUCHI KUNIHIKO
IPC分类号： G11C11/416 , H03K19/0175 , H03K19/08
摘要： PROBLEM TO BE SOLVED: To shorten the charging and discharging time of an output signal line and a cycle time by obtaining a discharging circuit which can make cycles fast by supplying the output current signal of a voltage-current converting means to a resistance element or load element. SOLUTION: The voltage-current converting means VIC1 is provided which converts the voltage of an input signal. IN11 or IN12 or the output signal of a logic gate LG1 receiving the input signal and the output current signal of this voltage-current converting means VIC1 is supplied to the resistance element or load element RB1. Then the base potential of a npn type bipolar transistor QDC1 for discharging is controlled with the output current signal of the voltage- current converting means VIC1. To actualize both charging and discharging, the QDC1, resistance element RB1, voltage-current converting means VIC1, and a common current source IDC are used for the npn type bipolar transistor, thereby actualizing fast discharging.

2. 发明专利

JPH11339479A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH11339479A
公开(公告)日：1999-12-10
申请号：JP14067498
申请日：1998-05-22
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD , HITACHI DEVICE ENG
发明人： KANETANI KAZUO , NANBU HIROAKI , YAMAZAKI SU , OHATA KENICHI , ARAKAWA FUMIHIKO , KUSUNOKI TAKESHI , HIGETA KEIICHI , NISHIYAMA MASAHIKO , YAMAGUCHI KUNIHIKO
IPC分类号： G11C11/413 , G11C11/414
摘要： PROBLEM TO BE SOLVED: To limit the level of a control signal for a switch discharging a signal line selectively below the withstanding voltage of the switch while guaranteeing that no discharge current flow through the signal line during nondischarging period thereof. SOLUTION: The semiconductor integrated circuit comprises a first bipolar transistor QDC having emitter connected with a current source IDC and collector connected with a load W, a switch MN having one end connected with the load and the other end connected with the base of the transistor, and a logic circuit D for controlling the current flowing through a first bipolar transistor QDC into the load W by turning the switch MN on/off. The semiconductor integrated circuit further comprises a level shift circuit LS receiving the output from the logic circuit D and the output of the level shift circuit LS is connected with the control terminal of the switch MN.

3. 发明专利

JPH11328970A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH11328970A
公开(公告)日：1999-11-30
申请号：JP13645398
申请日：1998-05-19
申请人： HITACHI LTD , HITACHI DEVICE ENG , HITACHI ULSI SYS CO LTD
发明人： NANBU HIROAKI , KANETANI KAZUO , YAMAZAKI SU , OHATA KENICHI , ARAKAWA FUMIHIKO , KUSUNOKI TAKESHI , HIGETA KEIICHI , NISHIYAMA MASAHIKO , YAMAGUCHI KUNIHIKO , SAEKI TETSUYA
IPC分类号： G11C11/41 , G11C11/413
摘要： PROBLEM TO BE SOLVED: To achieve reduction in power consumption and a cycle time of a semiconductor memory incorporating a writing pulse generation circuit. SOLUTION: A frequency-divided signal DDI dividing a clock pulse is compared with an output signal of a pseudo-memory cell in a comparison circuit CMP to make a dummy writing signal to '1', and inverse writing is performed in a pseudo-memory cell by the frequency-divided signal concurrently with this, and the dummy writing signal is returned to '0' by the comparison circuit to which the reversing signal and the frequency-divided signal of the pseudo- memory cell are inputted. Instead of a signal changed over twice a cycle as a signal for controlling the reverse writing in the pseudo-memory cell, a frequency-divided signal changed over only once a cycle is used. And, an operation delay time of the comparison circuit is not included in the pulse width of the dummy writing signal. As a result, it is possible to reduce the electric power consumed by the electrical charge and discharge of the dummy bit line to a half of a conventional one, and also shorten the cycle time.

4. 发明专利

JP2003242799A SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
公开(公告)号：JP2003242799A
公开(公告)日：2003-08-29
申请号：JP2002034652
申请日：2002-02-12
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： TOMIZAWA MASAHIKO , NISHIYAMA MASAHIKO
IPC分类号： G01R31/28 , G11C11/413 , G11C29/00 , G11C29/48 , G11C29/50 , H03K19/00
摘要： PROBLEM TO BE SOLVED: To enable a semiconductor chip to be trimmed after being sealed in a package. SOLUTION: This circuit comprises a control means performing mode switching about trimming or evaluation of an internal circuit. This control means comprises a control section (208) which can realize mode switching control about the trimming and the evaluation with a means of JTAG, the control section can perform trimming after a semiconductor chip is sealed in a package by constituting comprising an instruction decoding section for decoding an inputted instruction, a shift scan register group for enabling boundary scan based on a decoding result in the instruction decoding section, and an operation control section for controlling operation of the instruction decoding section and the shift register section. COPYRIGHT: (C)2003,JPO

5. 发明专利

JPH11250669A SEMICONDUCTOR DEVICE AND DATA PROCESSING SYSTEM 失效
公开(公告)号：JPH11250669A
公开(公告)日：1999-09-17
申请号：JP4648398
申请日：1998-02-27
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： KUSUNOKI TAKESHI , OHATA KENICHI , ARAKAWA FUMIHIKO , NANBU HIROAKI , KANETANI KAZUO , YAMAZAKI SU , HIGETA KEIICHI , NISHIYAMA MASAHIKO
IPC分类号： G11C11/413
摘要： PROBLEM TO BE SOLVED: To reduce a chip occupying area by a circuit configuration for giving a voltage from a test external terminal to a memory cell at the time of screening by giving an output voltage from an internal power source voltage generator to the cell in a normal operating time state. SOLUTION: An external terminal VEXT directly led from a power source supply line VCM of a memory cell out of a chip is provided. And, an internal power source voltage generator VCMG has a function of an output terminal OUT to a high impedance state. Thus, an insertion of a MOS switch in series between the power source supply line of the cell, the internal power source voltage generator and a testing external terminal is not required. No voltage drop occurs at the switch. And, a chip occupying area of the circuit for giving an operating power to the cell can be reduced.

6. 发明专利

JP2006236515A Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：JP2006236515A
公开(公告)日：2006-09-07
申请号：JP2005052250
申请日：2005-02-28
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： AIHARA YOICHIRO , NISHIYAMA MASAHIKO , SASAKI DAISUKE
IPC分类号： G11C29/10 , G11C15/04 , G11C29/12
CPC分类号： G11C29/36 , G01R31/31723 , G01R31/31813 , G11C15/00 , G11C2029/3602
摘要： PROBLEM TO BE SOLVED: To provide a means by which wiring channel regions relating to signal distribution, quantity of buffers, FF, or the like, and the number of LSI pins can be reduced, and mounting to a chip can be facilitated, in a built-in type self test circuit (BIST) for testing a CAM-macro.
SOLUTION: Data generators 104A, 104B, 104C for testing a CAM are inserted between an APG 101 for RAM and CAM-macros 105A, 105D, 105E, write-in data of the CAM-macros is generated from an address signal 12 directly or by decoding. The APG 101 is common for all memory-macros, an intrinsic test for the CAM can be performed by switching operation of the inserted data generators 104A, 104B, 104C by a control signal 14. The data generators 104A, 104B, 104C are arranged near the CAM-macros 105A, 105D, 105E being circuits to be tested.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种能够减少与信号分配，缓冲器数量，FF等相关的布线沟道区域和LSI引脚数量的装置，并且可以方便地安装到芯片，用于测试CAM宏的内置型自检电路（BIST）。解决方案：用于测试CAM的数据发生器104A，104B，104C插入在用于RAM的APG 101和CAM宏510A，105D，105E之间，从宏地址信号12生成CAM宏的写入数据直接或通过解码。 APG 101对于所有存储器宏是公用的，可以通过控制信号14切换插入数据发生器104A，104B，104C的操作来执行CAM的内在测试。数据发生器104A，104B，104C被布置在 CAM-宏105A，105D，105E是要测试的电路。版权所有（C）2006，JPO＆NCIPI

7. 发明专利

JP2003157676A SEMICONDUCTOR MEMORY 审中-公开
公开(公告)号：JP2003157676A
公开(公告)日：2003-05-30
申请号：JP2001357936
申请日：2001-11-22
申请人： HITACHI LTD
发明人： NISHIYAMA MASAHIKO , MITSUMOTO KINYA
IPC分类号： G11C11/41 , G06F12/00 , G06F12/06 , G11C11/413 , G11C11/417
摘要： PROBLEM TO BE SOLVED: To further improve access speed in a semiconductor memory adopting a late select system to which a lower order bit selecting way of a memory cell array out of read-out addresses is inputted late. SOLUTION: This device is provided with a plurality of data selectors 31, 32 selecting respectively either of a plurality of read-out data read from a plurality of ways and write data held in a WD register 41 for the late select system, and a way selector 35 selecting way data specified by a way selecting signal SAS inputted at read-cycle out of a plurality of outputs of these data selector 31, 32 and passing through them to an output side, further provided with a logic circuit 30 generating a signal by which a data selector of a way side specified by a write address SA of the WL register 13 selects a held write data side when the read-out address SA inputted at read-cycle coincides with a corresponding bit of a write address held in the WA register 13.

8. 发明专利

JP2002175692A SEMICONDUCTOR MEMORY AND DATA PROCESSING SYSTEM 失效
公开(公告)号：JP2002175692A
公开(公告)日：2002-06-21
申请号：JP2000372243
申请日：2000-12-07
申请人： HITACHI LTD
发明人： NISHIYAMA MASAHIKO , MITSUMOTO KINYA , AGARI TAKESHI
IPC分类号： G11C11/413 , G06F12/00 , G06F12/16 , G11C7/10 , G11C7/22 , G11C11/407 , G11C11/41
摘要： PROBLEM TO BE SOLVED: To reduce logic scale for generating a burst address and preventing malfunction in a memory provided with a rate-write function and having a DDR(Double Data Rate) mode. SOLUTION: In a SRAM(Static Random Access Memory) (1) having a DDR mode, even when a read-address coincides with a burst address of the preceding write-cycle by an address comparing means (30) comparing and discriminating whether a specified memory address externally supplied for read-out operation or its burst address coincides with the specified memory address of data latched by the preceding write-in cycle or its burst address or not, read-data of the burst address of the above coincidence is outputted to the read-address, even if rewriting is scheduled, data being not written in a memory cell never be read out. The address comparing means comprises basically combination circuits, also, does not generates directly a next memory address, the next memory address is not required to be held directly by an order circuit, and logic scale is reduced.

9. 发明专利

JPH09127205A MEASURING METHOD FOR ACCESS TIME 失效
公开(公告)号：JPH09127205A
公开(公告)日：1997-05-16
申请号：JP30982195
申请日：1995-11-02
申请人： HITACHI LTD
发明人： NISHIYAMA MASAHIKO , HIGETA KEIICHI , FUJIMURA YASUHIRO
IPC分类号： G01R31/28 , G11C29/00 , G11C29/56
摘要： PROBLEM TO BE SOLVED: To obtain a measuring method in which the accuracy of an access time measurement is enhanced. SOLUTION: On the basis of the difference between the timing of a clock signal CK0 at a time when the clock signal CK0 is delayed in a very small time unit and when a target signal state is latched by an SM latch circuit 11 and the timing of a clock signal CK1 at a time when the clock signal CK1 is delayed in a very small time unit and when a target signal state is latched by an SM latch circuit 12, the difference in an electric length between conductive lines L1, L3 at the outside of an LSI 15 is found regarding the clock signals CL0, CK1. When the difference in the electric length is corrected, an error in an access time measurement due to the difference in the electric length is reduced, and the accuracy of the access time of an SRAM part 13 is enhanced.

10. 发明专利

JP2012175012A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2012175012A
公开(公告)日：2012-09-10
申请号：JP2011037776
申请日：2011-02-24
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： TAKAGI TAKUMI , SASAKI DAISUKE , NISHIYAMA MASAHIKO , HASEGAWA MASATOSHI
IPC分类号： H01L27/11 , G11C11/41 , G11C11/413 , H01L21/8244 , H01L27/10
CPC分类号： G11C11/417
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having an SRAM macro with a power supply interruption function in which the design accompanied by an increase or decrease of storage capacity is facilitated.SOLUTION: In the semiconductor device, a memory array where multiple memory cells of SRAM are arranged, a first peripheral circuit which writes data in the memory array and reads data therefrom, and multiple units of layout each including a switch group for interrupting connection of the memory array and the first peripheral circuit with a power supply line are arranged.

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