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1. 发明专利

JP2011096363A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2011096363A
公开(公告)日：2011-05-12
申请号：JP2010280321
申请日：2010-12-16
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： HIGETA KEIICHI , IWAHASHI MASAYUKI , AIHARA YOICHIRO , NAKAHARA SHIGERU
IPC分类号： G11C15/04 , H01L21/8244 , H01L27/10 , H01L27/11
摘要： PROBLEM TO BE SOLVED: To reduce the area of a memory cell in a CAM. SOLUTION: A first memory (MA) and a second memory (MB) share data lines (D0, D1). A first transistor (MC0) connected to a first comparing data line (CD0) and a second transistor (MCA) connected to the storage node of the first memory are connected in series to form a first comparison circuit (11). A third transistor (MC1) connected to a second comparing data line (CD1) and a fourth transistor (MCB) connected to the storage node of the second memory are connected in series to form a second comparison circuit (12). Symmetry in the layout on a diffusion layer and wiring layer is improved. The memory cell is laid out easily in line symmetry with respect to the centerline passing through its center. Thus, the manufacturing process conditions are easily optimized, variability of the manufacturing process is reduced, and the memory cells can be made compact. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：减少CAM中存储单元的面积。解决方案：第一存储器（MA）和第二存储器（MB）共享数据线（D0，D1）。连接到连接到第一存储器的存储节点的第一比较数据线（CD0）和第二晶体管（MCA）的第一晶体管（MC0）串联连接以形成第一比较电路（11）。连接到连接到第二存储器的存储节点的第二比较数据线（CD1）和第四晶体管（MCB）的第三晶体管（MC1）串联连接以形成第二比较电路（12）。改善扩散层和布线层布局中的对称性。存储单元相对于穿过其中心的中心线容易地排列成对称的。因此，制造工艺条件容易优化，制造工艺的可变性降低，并且可以使存储单元紧凑。版权所有（C）2011，JPO＆INPIT

2. 发明专利

JP2006236515A Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：JP2006236515A
公开(公告)日：2006-09-07
申请号：JP2005052250
申请日：2005-02-28
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： AIHARA YOICHIRO , NISHIYAMA MASAHIKO , SASAKI DAISUKE
IPC分类号： G11C29/10 , G11C15/04 , G11C29/12
CPC分类号： G11C29/36 , G01R31/31723 , G01R31/31813 , G11C15/00 , G11C2029/3602
摘要： PROBLEM TO BE SOLVED: To provide a means by which wiring channel regions relating to signal distribution, quantity of buffers, FF, or the like, and the number of LSI pins can be reduced, and mounting to a chip can be facilitated, in a built-in type self test circuit (BIST) for testing a CAM-macro.
SOLUTION: Data generators 104A, 104B, 104C for testing a CAM are inserted between an APG 101 for RAM and CAM-macros 105A, 105D, 105E, write-in data of the CAM-macros is generated from an address signal 12 directly or by decoding. The APG 101 is common for all memory-macros, an intrinsic test for the CAM can be performed by switching operation of the inserted data generators 104A, 104B, 104C by a control signal 14. The data generators 104A, 104B, 104C are arranged near the CAM-macros 105A, 105D, 105E being circuits to be tested.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种能够减少与信号分配，缓冲器数量，FF等相关的布线沟道区域和LSI引脚数量的装置，并且可以方便地安装到芯片，用于测试CAM宏的内置型自检电路（BIST）。解决方案：用于测试CAM的数据发生器104A，104B，104C插入在用于RAM的APG 101和CAM宏510A，105D，105E之间，从宏地址信号12生成CAM宏的写入数据直接或通过解码。 APG 101对于所有存储器宏是公用的，可以通过控制信号14切换插入数据发生器104A，104B，104C的操作来执行CAM的内在测试。数据发生器104A，104B，104C被布置在 CAM-宏105A，105D，105E是要测试的电路。版权所有（C）2006，JPO＆NCIPI

3. 发明专利

JP2005197345A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2005197345A
公开(公告)日：2005-07-21
申请号：JP2004000316
申请日：2004-01-05
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： HIGETA KEIICHI , IWAHASHI MASAYUKI , AIHARA YOICHIRO , NAKAHARA SHIGERU
IPC分类号： G11C15/04 , G11C16/04 , H01L21/8244 , H01L27/11
CPC分类号： H01L27/11 , G11C15/04 , G11C15/043 , H01L27/1104
摘要： PROBLEM TO BE SOLVED: To reduce the area of a memory cell in a CAM. SOLUTION: Data lines (D0 and D1) are held in common with a first storage (MA) and a second storage (MB). A first transistor (MC0) connected to a first comparison data line (CD0) and a second transistor (MCA) connected at a storage node for the first storage are connected in series and a first comparison circuit (11) is formed. A third transistor (MC1) connected to a second comparison data line (CD1) and a fourth transistor (MCB) connected at the storage node for the second storage are connected in series, and a second comparison circuit (12) is formed. Accordingly, symmetries in layouts for a diffusion layer and a wiring layer are improved, and the layout forming the memory cell in a line symmetry to a center line passing through the center of the memory cell is attained easily. Consequently, the conditions of a manufacturing process are optimized easily, the dispersion of the manufacturing process is reduced, and the fining of the memory cell is attained. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：减少CAM中存储单元的面积。解决方案：数据线（D0和D1）与第一存储（MA）和第二存储（MB）保持共同。连接到连接在第一存储器的存储节点处的第一比较数据线（CD0）和第二晶体管（MCA）的第一晶体管（MC0）串联连接，形成第一比较电路（11）。连接到连接在第二存储器的存储节点处的第二比较数据线（CD1）和第四晶体管（MCB）的第三晶体管（MC1）串联连接，形成第二比较电路（12）。因此，扩散层和布线层的布局的对称性得到改善，并且容易地实现了形成与通过存储单元的中心的中心线对称的线的布局的布局。因此，容易地优化制造工序的条件，降低制造工序的分散性，能够实现存储单元的精细化。版权所有（C）2005，JPO＆NCIPI

4. 发明专利

JP2012099902A Mobile communication terminal 审中-公开
标题翻译：移动通信终端
公开(公告)号：JP2012099902A
公开(公告)日：2012-05-24
申请号：JP2010243596
申请日：2010-10-29
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： AIHARA YOICHIRO , MAZAWA SHIRO
IPC分类号： H04W76/04 , H04M1/00 , H04W76/06 , H04W88/02
摘要： PROBLEM TO BE SOLVED: To enable a mobile communication terminal performing data communication to quickly restart data communication after terminating a voice call service, when connection of the mobile communication terminal has been switched to a voice call system.SOLUTION: When connection of a mobile communication terminal 100 making call connection to a data communication system is switched to a voice call system, the mobile communication terminal uses the time released by cancelling packet transmission of a voice call to transmit control signals for maintaining or cancelling the call connection of data communication.
摘要翻译：要解决的问题：为了使移动通信终端在终止语音呼叫服务之后进行数据通信，能够快速重启数据通信，当移动通信终端的连接已被切换到话音呼叫系统时。解决方案：当将与数据通信系统进行呼叫连接的移动通信终端100的连接切换到语音呼叫系统时，移动通信终端使用通过取消语音呼叫的分组传输而释放的时间来发送用于维护或取消数据通信的呼叫连接。版权所有（C）2012，JPO＆INPIT

5. 发明专利

JPH08147996A REDUNDANCY SAVING METHOD, REDUNDANCY SAVE CIRCUIT AND SEMICONDUCTOR STORAGE 失效
公开(公告)号：JPH08147996A
公开(公告)日：1996-06-07
申请号：JP30278394
申请日：1994-11-11
申请人： HITACHI LTD
发明人： AIHARA YOICHIRO , HIGETA KEIICHI , YAMAGUCHI KUNIHIKO
IPC分类号： G11C11/413 , G11C11/401 , G11C29/00 , G11C29/04 , H01L21/82
摘要： PURPOSE: To provide a technique for reducing the chip occupancy area of a circuit for saving redundancy and improving yield. CONSTITUTION: By performing a redundancy word save in plural word lines, a row system inhibit theory 4 for invalidating normal word line selection is shared with plural word lines, and the yield is improved by suppressing increase of the scale of an inhibit circuit incorporating the row system inhibit theory and the increase of the chip occupancy area.

6. 发明专利

JPH0991996A SEMICONDUCTOR INTEGRATED CIRCUIT AND TEST EQUIPMENT THEREFOR 失效
公开(公告)号：JPH0991996A
公开(公告)日：1997-04-04
申请号：JP24197795
申请日：1995-09-20
申请人： HITACHI LTD
发明人： AIHARA YOICHIRO , HIGETA KEIICHI , MIYAMOTO KAZUHISA , YAMAGUCHI KUNIHIKO
IPC分类号： G01R31/28 , G11C29/00 , G11C29/02 , G11C29/06 , H01L21/66 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L27/092
摘要： PROBLEM TO BE SOLVED: To enhance the detection rate of failure by facilitating the burn-in test for both memory circuit and logic circuit and making possible both the burn-in test based on an internally generated test pattern and a diagnostic test based on an externally inputted test pattern. SOLUTION: In a semiconductor integrated circuit comprising a memory circuit and a logic circuit, a circuit 5b generating a test pattern (an address signal and a data signal) for the memory circuit and a circuit 5a generating a test pattern for logic circuit are provided on one chip. Switching can be made between a test pattern generated from the test pattern generating circuit 5b and an externaly provided test pattern.

7. 发明专利

JPH08138398A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH08138398A
公开(公告)日：1996-05-31
申请号：JP29576194
申请日：1994-11-04
申请人： HITACHI LTD
发明人： USAMI MASAMI , HIGETA KEIICHI , IWABUCHI MASATO , AIHARA YOICHIRO , YAMAGUCHI KUNIHIKO
IPC分类号： G11C11/413 , G11C29/00 , G11C29/04
摘要： PURPOSE: To enhance the efficiency of fault relieving due to redundancy construction. CONSTITUTION: A defect present in one memory mat is remedied by sharing redundant bit lines BL0', BL0'*, BL1', BL1'*, present in adjacent mats, between adjacent memory mats MM0 and MM1. Since the redundant bit line of adjacent memory mat can be used, the number of redundant bit lines is decreased and the efficiency of redundancy function is enhanced. Furthermore, the area of semiconductor chip is decreased while increasing the fabrication yield thereof.

8. 发明专利

JPH11250671A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH11250671A
公开(公告)日：1999-09-17
申请号：JP6217998
申请日：1998-02-26
申请人： HITACHI LTD
发明人： AIHARA YOICHIRO
IPC分类号： G11C11/413 , G11C29/00 , G11C29/04
摘要： PROBLEM TO BE SOLVED: To reduce a chip size by constituting a cache memory or the like of a computer, and enlarging a timing margin of a very high speed static RAM or the like having a plurality of memory units and redundant bit lines. SOLUTION: A Y redundant circuit for constituting a redundant memory unit having unit number of redundant bit lines and selectively designating a redundant bit line has cross-connected P-channel MOSFETSPb and Pc, P-channel MOSFETSPa and Pd for receiving internal clock signal PC, N-channel MOSFETSNa to Ni for respectively receiving redundant address signals SY0 to SY3, SU0 to SU3 or redundant enable signals REN0, N-channel MOSFETNj connected at its gate to an internal node n1, and P-channel MOSFETPe and N-channel MOSFETNk for receiving internal clock signals PC. And, its input terminal is connected to an internal node n2, its output signal contains a logic gate to become a redundant unit select signal R0 in one stage structure redundant address comparator ACP0 as a center.

9. 发明专利

JPH08236712A SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF DESIGNING IT 失效
公开(公告)号：JPH08236712A
公开(公告)日：1996-09-13
申请号：JP3857995
申请日：1995-02-27
申请人： HITACHI LTD
发明人： ANDO KAZUMASA , FUJIMURA YASUHIRO , AIHARA YOICHIRO
IPC分类号： H01L21/82 , H01L27/10
摘要： PURPOSE: To reduce power consumption at an unnecessary bit line without affecting the characteristics of a bit line clamp circuit by dividing a regulated current source of a bit line clamp circuit provided for each bit line into two parts to connect one regulated current source with non-used bit lines while separating the other regulated current source. CONSTITUTION: In an emitter follower part of a bit line clamp circuit 14 between two sets of regulated current sources 111, 112 and 121, 122 there are separated the latter sources. The remaining sources 111, 112 are designed to permit such a small current as 0.2mA to flow therethrough while the separated sources 121, 122 being designed to permit such a current as 0.6mA to flow therethrough. Accordingly, the bit line clamp circuit 14 corresponding to non-used bit lines has a consumed current reduced to about 1/4 compared with the bit line clamp circuit corresponding to the used bit lines. Further, since the regulated current sources 111, 112 are left behind in the bit line clamp circuit 14, potential of the non-used bit lines 15 is restricted not to float.

10. 发明专利

JPH11289047A MULTI-CHIP MODULE ITS AND MANUFACTURE 失效
公开(公告)号：JPH11289047A
公开(公告)日：1999-10-19
申请号：JP8978898
申请日：1998-04-02
申请人： HITACHI LTD
发明人： AIHARA YOICHIRO , HIGETA KEIICHI
IPC分类号： H01L25/18 , H01L23/52 , H01L25/065 , H01L25/07
摘要： PROBLEM TO BE SOLVED: To shorten a signal propagation delay time between chips, and to improve chip mounting density. SOLUTION: A multi-chip module on which plural processor are mounted is constituted of plural semiconductor chips 1 laminated in a two layer structure and a substrate 2 on which the semiconductor chip 1 in the laminated structure is mounted, and the electric connection of the semiconductor chip 1 with the substrate 2 is withdrawn from a semiconductor chip 1a in the upper layer. The semiconductor chip 1 is formed so that the positions of the overlapped semiconductor chip 1a in the upper layer and semiconductor chip 1b in the lower layer can be shifted, and the overlapped pads can be directly connected through solder balls 3. Also, the substrate 2 is formed so that the surface can be shaped like projection and recession, and the semiconductor chip 1b in the lower layer is mounted at the recessed part 2a upside down, and the wiring of a signal and a power source is connected through the solder balls 3 with the pad of the semiconductor chip 1a in the upper layer at the projecting part 2b.

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