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1. 发明专利

JPH0236631A BIT PHASE SYNCHRONIZING CIRCUIT 失效
公开(公告)号：JPH0236631A
公开(公告)日：1990-02-06
申请号：JP18563688
申请日：1988-07-27
申请人： HITACHI LTD , HITACHI COMMUNICATION SYSTEM
发明人： NISHI YUMIKO , KOMATSU AYAFUMI , TORII YUTAKA , TAKAGI SEIICHI
IPC分类号： H04L7/00
摘要： PURPOSE:To reduce the effect of dispersion in a gate delay time by ORing with a double clock and inverse of the double clock and using a clock so as to extract the signal being the result of ORing of the said outputs. CONSTITUTION:A clock inverse of 2ck and a data D1 are supplied to two input terminals of an AND gate 41 in an output gate extraction section 40 and a clock 2ck and a data D2 are given to two input terminals of an AND gate 42. Since the clocks 2ck, inverse of 2ck reach an H level alternately, the data D1, D2 are given to an OR gate 52 of an output section 50. Output signals DA, DB of the AND gates 41, 42 are signals being the result of synchronizing the H level of the input signal DI with the clock 2ck. Then the signals DA, DB inputted to the output section 50 are ORed by an OR gate 52, the result is a signal DD synchronously with the clock ck, the signal DD is extracted just in the center by using the clock, inverse of ck by a flip-flop 51 and the result becomes an output data DO. Thus, the effect due to the dispersion in the gates is avoided.

2. 发明专利

JPH01320841A BIT PHASE SYNCHRONIZING CIRCUIT 失效
公开(公告)号：JPH01320841A
公开(公告)日：1989-12-26
申请号：JP15232088
申请日：1988-06-22
申请人： HITACHI LTD , HITACHI COMMUNICATION SYSTEM
发明人： NISHI YUMIKO , KOMATSU AYAFUMI , TORII YUTAKA , TAKAGI SEIICHI
IPC分类号： H04J3/06 , H04L7/00
摘要： PURPOSE:To increase a margin with respect to the fluctuation of an input signal and the stability in a short period by segmenting each input signal at the leading of a clock divided in n-phase and fetching an input data in the clock of (i+l)th phase when the value segmented by the clock of the i-th phase shows H at first. CONSTITUTION:In the presence of a path setting command, a set signal is outputted synchronously with the leading of an input data DI, gates of three FFs 21, 22, 23 of a data latch section 20 are opened and an input data DI' is inputted. This is fetched respectively by clocks CK 1, 2, 3 and let the outputs be D1, D2, D3, then supposing that D1=L, D2=H, D3=n exist, an optimum clock discrimination section 30 selects the clock CK 3 as the optimum clock by the algorithm. In this case, the leading of the clock CK 3 segmenting the 2nd H is regarded as to segment the center or its vicinity of the data DI'.

3. 发明专利

JP2002344535A SYSTEM AND METHOD FOR PROVIDING DATA TRANSMITTING SERVICE AND METHOD OF BUILDING THE SYSTEM 审中-公开
公开(公告)号：JP2002344535A
公开(公告)日：2002-11-29
申请号：JP2001297890
申请日：2001-09-27
申请人： HITACHI LTD , HITACHI COMMUNICATION SYSTEM
发明人： YAMAMOTO KOHEI , NAGUMO KATSUMI , SUZUKI SHINJI , NISHI YUMIKO , HATA MIKIHIKO
IPC分类号： H04J3/00 , H04L12/66
摘要： PROBLEM TO BE SOLVED: To provide data transmitting services to subscribers incorporated in a remote terminating device connected to an incorporated station through an STM transmission line. SOLUTION: A fixed band for data call is assigned to an exchange call processor 31, and a data call (STM data) 92 from an ADSL subscriber incorporated device 32 is sent to an optical cable 72 by assigning the call 92 to the fixed band. In addition, the data call (STM data) 92 assigned to the fixed band on the cable 72 is sent to the incorporated device 32. On the other hand, a route distributing device 44 provided in the incorporated station 4 distributes STM data (multiplexed signals 95) on the cable 72 to routes in accordance with the fixed band, and sends an exchange call (STM data) 91 to an exchange 41. At the same time, the data call (STM data) 92 is transmitted to an ADSL multiplexer 42.

4. 发明专利

JPH0685628A CLOCK CUT DETECTING CIRCUIT 失效
公开(公告)号：JPH0685628A
公开(公告)日：1994-03-25
申请号：JP23685392
申请日：1992-09-04
申请人： HITACHI LTD , HITACHI COMMUNICATION SYSTEM
发明人： KIKUCHI MINORU , NISHI YUMIKO
IPC分类号： H03K5/19 , G06F1/04 , H04L7/00
摘要： PURPOSE:To provide a clock cut detecting circuit consisting of a logical element and an integrated circuit. CONSTITUTION:A clock signal 1 to be detected is held by a flip-flop 4 as a detected clock signal 2 and inputted to the clock terminal of a 1-bit counter 6. The output of the counter 6 is turned into an alternating signal 7 which changes with transition to a high level from a low level of a signal 5. The signal 7 is synchronized with a detecting clock signal 3 through a flip-flop 8 and then delayed by a flip-flop 10. The states of the signals 9 and 11 are compared with each other by an exclusive OR circuit 12. When the signal 1 or 2 is cut, the transition of the signal 5 is stopped and the signal 7 is set at a fixed level. Under such conditions, the state of both signals 9 and 11 are coincident with each other and the output 13 of the circuit 12 is set at a low level. Thus a cut state of a detected clock signal can be detected.

5. 发明专利

JPH02237240A BIT PHASE SYNCHRONOUS CIRCUIT 失效
公开(公告)号：JPH02237240A
公开(公告)日：1990-09-19
申请号：JP5646289
申请日：1989-03-10
申请人： HITACHI LTD , HITACHI COMMUNICATION SYSTEM
发明人： NISHI YUMIKO , TAKAGI SEIICHI
IPC分类号： H04L7/00 , H04L7/033
摘要： PURPOSE:To widen a pulse width and to obtain a bit synchronous circuit which has a large operation margin and which fits for making it into LSI by making the operation speed of a clock to 1/2. CONSTITUTION:A latch part 10 latches an input data signal by the rise and fall of the clocks CK1-CK8 different in phases at a clock speed SHZ with respect to an input data signal speed 2Sb/s, and a detection part 20 detects the change phase of a data signal. A reproduction clock selection part 30 avoids the change point of the data signal by the detection result and selected the clock having the phase which can reproduce the data signal among the clocks CK1-CK8. A phase synchronous part 40 alternately punches the input data signal by the rise and fall of the reproduction clock, sets it to be two bit parallel data (Sb/s) which is phase-synchronized and a speed conversion part 50 converts two bit parallel data into serial data of the original speed (2Sb/s) again. Thus, the circuit with the large operation margin can be obtained for making it into LSI.

6. 发明专利

JPH0236630A BIT PHASE SYNCHRONIZING CIRCUIT 失效
公开(公告)号：JPH0236630A
公开(公告)日：1990-02-06
申请号：JP18563588
申请日：1988-07-27
申请人： HITACHI LTD , HITACHI COMMUNICATION SYSTEM
发明人： NISHI YUMIKO , KOMATSU AYAFUMI , TORII YUTAKA , TAKAGI SEIICHI
IPC分类号： H04L7/00
摘要： PURPOSE:To select a reproduced clock optimum to an input signal in a shorter time by regenerating a reproducing signal synchronously with the same clock in a high speed signal inputted in a different phase by means of a system common clock. CONSTITUTION:An output section 40 has flip-flops 41-43 whose reset terminals connect to outputs S1-S3 of flip-flops 31-33 of an optimum clock discrimination section 30, an input signal DI is given in common to each input terminal and clocks CK1-CK3 are given respectively to clock terminals. Then an input signal D2 reproduced by the flip-flop 42 is regenerated at a flip-flop 44 by using the clock CK1 into a reproducing signal D2'. Thus, the reproduced signal is regenerated by using the common system clock to obtain an output signal synchronously with the system clock. Thus, a high speed input signal including jitter is regenerated by using the optimum clock in a short time.

7. 发明专利

JPH01231449A BIT PHASE SYNCHRONIZING CIRCUIT 失效
公开(公告)号：JPH01231449A
公开(公告)日：1989-09-14
申请号：JP5608188
申请日：1988-03-11
申请人： HITACHI LTD , HITACHI COMMUNICATION SYSTEM
发明人： NISHI YUMIKO , TORII YUTAKA , KOMATSU AYAFUMI , TAKAGI SEIICHI
IPC分类号： H04J3/06 , H04L7/00 , H04L7/02
摘要： PURPOSE:To reduce the effect of dispersion in a gate delay time by using a recovered clock so as to segment a data signal as a recovered data signal and giving proper delay to the recovered data signal and using a system clock so as to apply segmentation again. CONSTITUTION:Since a latch section 10 latches a data signal by a clock with different phase, a detection section 20 detects a changed phase in the data signal from the result. The detection section 20 detects the signal for a prescribed time and stores the change of phase detected so far. A recovery clock selection circuit 30 based on the result of detection selects a clock having a phase offering stable data signal recovery while avoiding the point of time in the change of the data signal among (n)-kind of clocks. A synchronizing section 40 uses the recovered clock to segment the data signal as a recovered data and gives a proper delay to the recovered data so that the data is segmented stably by the system clock and uses the system clock to segment the recovered data while avoiding the changing point of time of the data. Thus, the effect of the dispersion in the gate delay time is reduced.

8. 发明专利

JP2002058060A SIGNAL CONTROL METHOD 失效
公开(公告)号：JP2002058060A
公开(公告)日：2002-02-22
申请号：JP2000238466
申请日：2000-08-07
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： YAMAMOTO KOHEI , FUKUSHIMA YUTAKA , NISHI YUMIKO , TSUKIOKA YOICHI , NANBA YUKIHIRO
IPC分类号： H04M3/42 , H04M3/00 , H04M11/00 , H04W24/04 , H04W84/14 , H04Q7/36
摘要： PROBLEM TO BE SOLVED: To realize a various information transmitting service such as a calling telephone number receiving function service while securing the subscriber's circuit control signal transmission and reception timing of the service and protecting the subscriber's circuit control signal from any data transmission error by shortening a delay time in a radio section. SOLUTION: At the time of performing cabling between inter-protocol converter 2a and WAC 3a and calling inside FWA system 7a, a voice signal transmitting line 23a and a subscriber's circuit control signal transmission and receiving line 24a are secured for transmitting and receiving a outgoing subscriber's circuit control signal in a proper format such as a bit map format. Moreover, a control signal monitor control unit 13a is provided with a buffer 14a for temporarily storing an outgoing subscriber's circuit control signal 18a in a proper format such as a bit map format to be received from the subscriber's circuit control signal transmitting and receiving line 24a, an incoming monitoring part 15 for detecting the secondary response signal of an incoming subscriber's circuit control signal 21b, an L1 and L2 polarity depolarization preparing part 16a for preparing L1 and L2 polarity depolarization to be outputted to a subscriber's circuit 6a at the time of detecting the secondary response signal, and an MF switching part 17a for switching the outgoing subscriber's circuit control signal 21a to be transmitted to the subscriber's circuit 6a.

9. 发明专利

JPH07231354A EXTENSION CALL TERMINATING SYSTEM USING VOICE RECOGNIZING DEVICE 失效
公开(公告)号：JPH07231354A
公开(公告)日：1995-08-29
申请号：JP2012594
申请日：1994-02-17
申请人： HITACHI LTD
发明人： OGISO HISASHI , SAKURAI YOSHITO , NISHI YUMIKO , TONOMURA SACHIKO , OGAWA TARO
IPC分类号： H04M3/50 , H04M3/42 , H04Q3/58
摘要： PURPOSE:To more economically provide a service improving function like automatic extension connection service by using a voice recognizing device installed inside an intelligent network. CONSTITUTION:Between a service switching point 4 as an exchange connected to a call originating terminal 6 and provided with a gateway function and a service control point 1 as a communication control center for executing information processing/data base control, an additional device 3 is installed to process special service which can not be executed by the service switching point 4. Further, at this position, a voice recognizing device 9 is installed by providing functions for receiving an instruction to recognize the voice of a subscriber to the service control point 1, converting it to a name code by the additional device 3 and transmitting it to the service control point 1.

10. 发明专利

JPH04207380A IMAGE COMMUNICATION SYSTEM 失效
公开(公告)号：JPH04207380A
公开(公告)日：1992-07-29
申请号：JP32911790
申请日：1990-11-30
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： NISHI YUMIKO , GOTO HIROSHI , YOSHIDA MITSUO , YASUDA MINORU , SUZUKI HAJIME
IPC分类号： H04N11/04 , H03M7/40 , H04N7/10 , H04N7/24 , H04N19/00 , H04N19/42 , H04N19/423 , H04N19/85
摘要： PURPOSE:To facilitate change of variables installing a RAM capable of direct writing from the terminal of an operating section in the digital signal processing sections existing in a signal receiving section and a signal transmitting section. CONSTITUTION:Analog image information is inputted to the signal transmitting section 10 where the information is converted to a digital signal. The digital signal is encoded by using the prescribed variable in the digital signal processing section 112 and is inputted through a digital network 40 to the signal receiving section 20. The signal is decoded to the analog signal by using the prescribed variable in the digital signal processing section 212. The analog signal is inputted to the operating section 30. The variables, such as table value parameter, necessary for encoding and decoding are written into the RAM in the digital signal processing sections 112, 212 from a disk 33 possessed by the operating section 30. The change of the variables arising from the improvement of the image quality is easily executed in this way from the operating section 30.

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