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1. 发明专利

JPH0236631A BIT PHASE SYNCHRONIZING CIRCUIT 失效
公开(公告)号：JPH0236631A
公开(公告)日：1990-02-06
申请号：JP18563688
申请日：1988-07-27
申请人： HITACHI LTD , HITACHI COMMUNICATION SYSTEM
发明人： NISHI YUMIKO , KOMATSU AYAFUMI , TORII YUTAKA , TAKAGI SEIICHI
IPC分类号： H04L7/00
摘要： PURPOSE:To reduce the effect of dispersion in a gate delay time by ORing with a double clock and inverse of the double clock and using a clock so as to extract the signal being the result of ORing of the said outputs. CONSTITUTION:A clock inverse of 2ck and a data D1 are supplied to two input terminals of an AND gate 41 in an output gate extraction section 40 and a clock 2ck and a data D2 are given to two input terminals of an AND gate 42. Since the clocks 2ck, inverse of 2ck reach an H level alternately, the data D1, D2 are given to an OR gate 52 of an output section 50. Output signals DA, DB of the AND gates 41, 42 are signals being the result of synchronizing the H level of the input signal DI with the clock 2ck. Then the signals DA, DB inputted to the output section 50 are ORed by an OR gate 52, the result is a signal DD synchronously with the clock ck, the signal DD is extracted just in the center by using the clock, inverse of ck by a flip-flop 51 and the result becomes an output data DO. Thus, the effect due to the dispersion in the gates is avoided.

2. 发明专利

JPH04199995A OPTICAL EXCHANGE 失效
公开(公告)号：JPH04199995A
公开(公告)日：1992-07-21
申请号：JP32598690
申请日：1990-11-29
申请人： HITACHI LTD , HITACHI COMMUNICATION SYSTEM
发明人： AIDA YASUO , KOMATSU AYAFUMI , TAKAGI SEIICHI , CHIBA YOSHIYUKI
IPC分类号： H04Q3/72 , H04M3/00 , H04Q3/52
摘要： PURPOSE:To detect a call with little malfunction by storing a call detection circuit in the output terminal of an output-side optical waveguide where the number of passing cross points becomes the largest when it is counted from the subscriber-side of the input-side optical waveguide of an optical switch. CONSTITUTION:The call detection circuit 72 is connected to the output-side waveguide 21 where the number of the passing cross points of an optical channel becomes the largest. The input terminal of the optical channel to which a subscriber from whom the call is not detected is connected from an output terminal 0ADD0 where the call detection circuit 72 is stored to the output terminal 0ADD1 nearer to an input terminal-side and all optical signals from non-call subscribers 82-84 are caused to flow to a trunk 91-side. Then, a leaking call amount in cross points 32-34 is reduced. Thus, only a call pattern from a caller 81 is inputted to the call detection circuit 72. Thus, erroneous call detection can be eliminated.

3. 发明专利

JPH03132124A BIT PHASE SYNCHRONIZING CIRCUIT 失效
公开(公告)号：JPH03132124A
公开(公告)日：1991-06-05
申请号：JP26897489
申请日：1989-10-18
申请人： HITACHI LTD , HITACHI COMMUNICATION SYSTEM
发明人： SUGITA NAOMI , KOMATSU AYAFUMI , SAKURAI TOSHIYA
IPC分类号： H04L7/00
摘要： PURPOSE:To stably maintain a bit synchronization state by providing a stabilizing protection circuit fetching a pulse representing non-bit phase synchronization state from a phase difference detection section independently of the period of a system clock, counting the pulse and outputting a selection control pulse when the counted value reaches the prescribed number of times. CONSTITUTION:A stabilizing protection circuit 23 is provided, in which a pulse representing a non-bit phase synchronization state outputted from a data clock phase difference section 22 is fetched as the clock of a counter and when the pulse is counted for a prescribed number of times, a data signal is subjected to selection control. That is, shift registers (23-1)-(23-3) in the stabilizing protection circuit 23 fetches a pulse representing a non-bit phase synchronization state from the data clock phase difference section 22 to latch a fixed data sequentially and outputs a pulse for data selection control when the count by the number of stages of FFs is counted and applies self-reset. Thus, the bit phase synchronization circuit is obtained, in which the detection period of the signal state change point of the data signal is not selected and bit phase synchronization state is maintained more stably against noise or the like, as well.

4. 发明专利

JPH02272987A METHOD OF DETECTING SWITCH TROUBLE 失效
公开(公告)号：JPH02272987A
公开(公告)日：1990-11-07
申请号：JP9288489
申请日：1989-04-14
申请人： HITACHI LTD , HITACHI COMMUNICATION SYSTEM
发明人： TAKAGI SEIICHI , KOMATSU AYAFUMI
IPC分类号： H04Q1/24
摘要： PURPOSE:To prevent the increase of the hardware quantity of a switch trouble detecting circuit even when the scale of a space disassembly switch is enlarged by comparing the values of two reversible counter, and when the fact that both values are not equal is decided, deciding a switch bus trouble and outputting a malfunction line address and an alarm signal. CONSTITUTION:An idle request and an idle release request outputted by an output interruption detecting circuit 5 provided for each outgoing line is the line use information of n-number of outgoing lines, and by always grasping the numbers of both by a reversible counter 8, the number of outgoing lines of an spatial division switch to be practical can be known. On the other hand, by counting a bus connecting signal and a bus releasing signal outputted with a control part 2 by a reversible counter 9, the using number of the outgoing lines of a spatial division switch 1 requested with the processor of an exchange can be known. By comparing the numerical values of two reversible counters 8 and 9, the trouble detection of the spatial disassembly switch 1 can be executed. Thus, even when the scale of the spatial division switch 1 is enlarged, the increase of the hardware quantity of the switch trouble detecting circuit can be suppressed to an irreducibly minimum.

5. 发明专利

JPH0353629A BIT PHASE SYNCHRONIZING CIRCUIT AND DATA TRANSMISSION EQUIPMENT 失效
公开(公告)号：JPH0353629A
公开(公告)日：1991-03-07
申请号：JP18736889
申请日：1989-07-21
申请人： HITACHI LTD , HITACHI COMMUNICATION SYSTEM
发明人： KOMATSU AYAFUMI , SUGITA NAOKI , SAKURAI TOSHIYA
IPC分类号： H04L7/00 , H04L7/02
摘要： PURPOSE:To attain stable bit phase synchronization even to an ultrahigh speed signal by outputting a data signal segmented around its pulse width center with a system clock based on the result of phase difference detection as an output data signal. CONSTITUTION:The bit phase synchronizing circuit consists of a data selection output section 20, a signal state change point detection section 21, a data clock phase difference detection section 22, a data selection control section 23 and a data output section 24. Every time a data signal is sequentially selected by the data selection output section 20, the relation of phase between a changing point of time of the state of the signal and leading and trailing point of time of a system clock is discriminated and when the relation is a prescribed relation, it is discriminated to be in the bit phase synchronizing state, the data signal is segmented at the leading or trailing of the system clock while the data signal is being selected. Thus, stable bit phase synchronization is attained even to an ultrahigh speed signal.

6. 发明专利

JPH01320841A BIT PHASE SYNCHRONIZING CIRCUIT 失效
公开(公告)号：JPH01320841A
公开(公告)日：1989-12-26
申请号：JP15232088
申请日：1988-06-22
申请人： HITACHI LTD , HITACHI COMMUNICATION SYSTEM
发明人： NISHI YUMIKO , KOMATSU AYAFUMI , TORII YUTAKA , TAKAGI SEIICHI
IPC分类号： H04J3/06 , H04L7/00
摘要： PURPOSE:To increase a margin with respect to the fluctuation of an input signal and the stability in a short period by segmenting each input signal at the leading of a clock divided in n-phase and fetching an input data in the clock of (i+l)th phase when the value segmented by the clock of the i-th phase shows H at first. CONSTITUTION:In the presence of a path setting command, a set signal is outputted synchronously with the leading of an input data DI, gates of three FFs 21, 22, 23 of a data latch section 20 are opened and an input data DI' is inputted. This is fetched respectively by clocks CK 1, 2, 3 and let the outputs be D1, D2, D3, then supposing that D1=L, D2=H, D3=n exist, an optimum clock discrimination section 30 selects the clock CK 3 as the optimum clock by the algorithm. In this case, the leading of the clock CK 3 segmenting the 2nd H is regarded as to segment the center or its vicinity of the data DI'.

7. 发明专利

JPH03101494A INPUT AND OUTPUT CIRCUIT 失效
公开(公告)号：JPH03101494A
公开(公告)日：1991-04-26
申请号：JP23707389
申请日：1989-09-14
申请人： HITACHI LTD , HITACHI COMMUNICATION SYSTEM
发明人： GOTO HIROSHI , KOMATSU AYAFUMI , SUGITA NAOMI , SAKURAI TOSHIYA
IPC分类号： H04Q3/52 , H04Q11/04
摘要： PURPOSE:To eliminate need for manual adjustment by decreasing a clock rate into 1/n for the connection to other package via a connector and reconstituting the rate into a clock rate caused in the package at a receiver side automatically. CONSTITUTION:A bit width of the output of output highways(HW)1A, 1B at the output side of a switch LSI is twice than the output of an output HW 16 and the output is connected to a switch LSI of other package via a connector whose passing signal speed is low. When the input signals via a connector are connected to the input HW1A, HW1B at the input side of the switch LSI, till data of both A, B are coincident, a selector SEL of 1/2 operation input highway sections 1, 2 is controlled and when they are coincident, the selector is made stable in this state. The output is entirely the same as the arrangement of a parallel data from the input HW16, multiplexed and written in a memory SPM. Thus, manual adjustment of the delay time is not required.

8. 发明专利

JPH02306794A TIME DIVISION SWITCH 失效
公开(公告)号：JPH02306794A
公开(公告)日：1990-12-20
申请号：JP12662589
申请日：1989-05-22
申请人： HITACHI LTD , HITACHI COMMUNICATION SYSTEM
发明人： SAKURAI TOSHIYA , KOMATSU AYAFUMI
IPC分类号： H04Q3/52 , H04Q11/04
摘要： PURPOSE:To relax a write time with respect to a storage memory and to quicken the exchange processing of a channel by utilizing an exchange processing time of the channel accommodating the information not requiring the exchange processing of the channel so as to write the storage memory. CONSTITUTION:A storage memory controller 14 detects a timing for writing of exchange control information to a channel of a storage memory 11 synchronously with a frame signal to apply write control of the channel exchange information to the storage memory. Since the highway control information is inserted at the post-stage of speech memories 5, 6 and extracted at the pre- stage of the speech memories 5, 6, the exchange processing of the channel in the speech memories 5, 6 is not required to invalidate the operation of the storage memory to the speech memories for a time when the information is processed thereby writing the exchange control information of the channel. Thus, even when the speed of the speech information is high, the use of the storage memory of the same operating speed is attained and the channel exchange processing is implemented quickly.

9. 发明专利

JPH0236630A BIT PHASE SYNCHRONIZING CIRCUIT 失效
公开(公告)号：JPH0236630A
公开(公告)日：1990-02-06
申请号：JP18563588
申请日：1988-07-27
申请人： HITACHI LTD , HITACHI COMMUNICATION SYSTEM
发明人： NISHI YUMIKO , KOMATSU AYAFUMI , TORII YUTAKA , TAKAGI SEIICHI
IPC分类号： H04L7/00
摘要： PURPOSE:To select a reproduced clock optimum to an input signal in a shorter time by regenerating a reproducing signal synchronously with the same clock in a high speed signal inputted in a different phase by means of a system common clock. CONSTITUTION:An output section 40 has flip-flops 41-43 whose reset terminals connect to outputs S1-S3 of flip-flops 31-33 of an optimum clock discrimination section 30, an input signal DI is given in common to each input terminal and clocks CK1-CK3 are given respectively to clock terminals. Then an input signal D2 reproduced by the flip-flop 42 is regenerated at a flip-flop 44 by using the clock CK1 into a reproducing signal D2'. Thus, the reproduced signal is regenerated by using the common system clock to obtain an output signal synchronously with the system clock. Thus, a high speed input signal including jitter is regenerated by using the optimum clock in a short time.

10. 发明专利

JPH01231449A BIT PHASE SYNCHRONIZING CIRCUIT 失效
公开(公告)号：JPH01231449A
公开(公告)日：1989-09-14
申请号：JP5608188
申请日：1988-03-11
申请人： HITACHI LTD , HITACHI COMMUNICATION SYSTEM
发明人： NISHI YUMIKO , TORII YUTAKA , KOMATSU AYAFUMI , TAKAGI SEIICHI
IPC分类号： H04J3/06 , H04L7/00 , H04L7/02
摘要： PURPOSE:To reduce the effect of dispersion in a gate delay time by using a recovered clock so as to segment a data signal as a recovered data signal and giving proper delay to the recovered data signal and using a system clock so as to apply segmentation again. CONSTITUTION:Since a latch section 10 latches a data signal by a clock with different phase, a detection section 20 detects a changed phase in the data signal from the result. The detection section 20 detects the signal for a prescribed time and stores the change of phase detected so far. A recovery clock selection circuit 30 based on the result of detection selects a clock having a phase offering stable data signal recovery while avoiding the point of time in the change of the data signal among (n)-kind of clocks. A synchronizing section 40 uses the recovered clock to segment the data signal as a recovered data and gives a proper delay to the recovered data so that the data is segmented stably by the system clock and uses the system clock to segment the recovered data while avoiding the changing point of time of the data. Thus, the effect of the dispersion in the gate delay time is reduced.

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