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1. 发明专利

JP2003167021A MANUFACTURING METHOD AND SHELL FOR SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：JP2003167021A
公开(公告)日：2003-06-13
申请号：JP2001368229
申请日：2001-12-03
申请人： HITACHI LTD , AKITA DENSHI SYSTEMS KK
发明人： KUSANAGI YOSHITOMO , SHIBATA TORU
IPC分类号： G01R31/26 , H01L21/66
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method for a semiconductor device, capable of accurately putting chips in a shell, preventing an offset phenomenon upon closing a cover of the shell, and radiating heat generated upon testing, and a shell for use in the method. SOLUTION: In this manufacturing method for the semiconductor device for manufacturing KGD chips such as a memory and a microcomputer logic and shipping the same, in a process of packing chips into the shell, when the shell is loaded with chips cut from a wafer and individually separated from each other, the chips are held by a holding means and put in the shell under high-accuracy position recognition by a position recognizing means on the device side (step S21), with the chips put in the shell and held to be fixed by the holding means, a body cover of the shell is closed (step S22), further a heat radiation cover formed by a heat radiative member as a part of the cover is closed, and the radiative member of the radiating cover is brought into contact with the chips put in the shell (step S23). COPYRIGHT: (C)2003,JPO

2. 发明专利

JPH07263473A SEMICONDUCTOR MOLDING MACHINE 失效
公开(公告)号：JPH07263473A
公开(公告)日：1995-10-13
申请号：JP4806694
申请日：1994-03-18
申请人： HITACHI LTD , AKITA DENSHI KK
发明人： KUSANAGI YOSHITOMO , WATABE SATOSHI
IPC分类号： B29C43/36 , B29C43/52 , B29C45/73 , B29L31/34 , H01L21/56
摘要： PURPOSE:To provide technique which can prevent occurrence of a void, a wire flow at the time of molding a semiconductor. CONSTITUTION:A semiconductor molding machine has molds 15 for molding a semiconductor, conveying means 14, 16 for conveying the semiconductor before and after molding, and resin storing means 12 for storing resin to be molded, and comprises means 11 for regulating a temperature of the resin in the means 12.

3. 发明专利

JPH04106942A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH04106942A
公开(公告)日：1992-04-08
申请号：JP22258990
申请日：1990-08-27
申请人： HITACHI LTD , AKITA DENSHI KK
发明人： ISHIZAWA TAMOTSU , KUSANAGI YOSHITOMO
IPC分类号： H01L21/60
摘要： PURPOSE:To enable excellent pellet bonding and wire bonding as well even when a heat block and a lead frame are under a poor contact state by installing a temperature detection mechanism and comparing the result of its measured temperature with a required proper temperature. CONSTITUTION:When a lead frame 5 is mounted on a head block 1 at a specified position, the heat of a main body of the heat block 1 is transmitted to the frame 5 by a heater 4. During the conduction of heat, an infrared temperature sensor 15 on the frame 5 senses the surface temperature of an inner lead of the frame 5 or a semiconductor pellet 8 or the like. The measured surface temperature is output into a control section 3 where the measured surface temperature is compared with a proper bonding temperature stored and the temperature difference is computed and output to the heater 4, thereby heating the block 1 under control to a desired temperature. This construction makes it possible to obtain excellent bonding even when a bonded material and the heat block are under a poor contact state.

4. 发明专利

JP2010171315A Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2010171315A
公开(公告)日：2010-08-05
申请号：JP2009014135
申请日：2009-01-26
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： TSUNODA SHIGEHARU , MATSUSHIMA NAOKI , AMANO YASUO , WATABE MITSUHISA , KUSANAGI YOSHITOMO
IPC分类号： H01L21/60 , H01L23/12
CPC分类号： H01L2224/11
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device in which a flexible substrate and a semiconductor chip can be aligned stably in a short time.
SOLUTION: The method of manufacturing the semiconductor device uses, as a flexible substrate 3, a flexible substrate 3 having a reinforcement structure 5 for improving the flexural rigidity of the substrate body, for alignment and joint with the semiconductor chip 1. The reinforcement structure 5 for improving the flexural rigidity of the substrate body makes it possible to improve the planarity of the flexible substrate, stabilize transport between the manufacturing steps, and align the substrate with the semiconductor chip 1 stably in a short time.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体器件的制造方法，其中可以在短时间内稳定地对准柔性基板和半导体芯片。解决方案：半导体器件的制造方法使用柔性基板3，该柔性基板3具有用于提高基板主体的抗弯刚度的加强结构5，用于与半导体芯片1对准和接合。用于提高基板主体的抗弯刚度的加强结构5使得可以在短时间内稳定地改善柔性基板的平面度，使制造步骤之间的输送稳定并且使半导体芯片1稳定地对准基板。版权所有（C）2010，JPO＆INPIT

5. 发明专利

JP2011054820A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2011054820A
公开(公告)日：2011-03-17
申请号：JP2009203425
申请日：2009-09-03
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： HASEBE TAKEHIKO , MATSUSHIMA NAOKI , TSUNODA SHIGEHARU , AMANO YASUO , TORIGOE MAKOTO , WATABE MITSUHISA , KUSANAGI YOSHITOMO
IPC分类号： H01L21/3205 , H01L23/32 , H01L23/52 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L25/0657 , H01L2224/48227 , H01L2225/0651 , H01L2225/06562 , H01L2924/10253 , H01L2924/13091 , H01L2924/15311 , H01L2924/3025 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a laminated package of thin semiconductor chips that has enhanced drive stability, improved yield in a lamination process, and has improved long-period reliability in a mounted state. SOLUTION: In the semiconductor package, a plurality of semiconductor chips 500 and 501, and an interposer 502 are laminated. Each of the semiconductor chip includes: a semiconductor element 110; wiring for supplying a signal to the semiconductor element 110; a signal electrode; a power supply electrode; and a ground electrode, on a chip top surface, and includes: a signal electrode; a power supply electrode; and a ground electrode, on a chip rear surface, and further includes: through wiring for electrically connecting the electrodes on the chip top surface and the electrodes on the chip rear surface to each other; and a conductor layer 120 covering the rear surface of the chip and connected to the ground electrode. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有增强的驱动稳定性，提高层叠工艺中的产量的薄半导体芯片的层叠封装，并且在安装状态下具有改善的长周期可靠性。解决方案：在半导体封装中，层叠多个半导体芯片500和501以及中介层502。半导体芯片中的每一个包括：半导体元件110; 用于向半导体元件110提供信号的布线; 信号电极; 电源电极; 以及在芯片顶面上的接地电极，包括：信号电极; 电源电极; 以及在芯片后表面上的接地电极，并且还包括：通过布线，用于将芯片顶表面上的电极和芯片后表面上的电极彼此电连接; 以及覆盖芯片的后表面并连接到接地电极的导体层120。版权所有（C）2011，JPO＆INPIT

6. 发明专利

JP2009218390A Semiconductor device, and manufacturing method thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2009218390A
公开(公告)日：2009-09-24
申请号：JP2008060797
申请日：2008-03-11
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： TANIE HISAFUMI , MORIYA HIROSHI , ANJO ICHIRO , KUSANAGI YOSHITOMO , WATABE MITSUHISA
IPC分类号： H01L25/04 , H01L25/18
CPC分类号： H01L2224/16225 , H01L2224/73253
摘要： PROBLEM TO BE SOLVED: To provide a high-reliability and high-density semiconductor device. SOLUTION: Semiconductor packages 3 on lower tiers are directly mounted on a board 1 to be electrically connected thereto, semiconductor packages 2 on upper tiers are mounted on the board 1 through first spacers 4 to be electrically connected to the board, and the semiconductor packages 2 on the upper tiers and the semiconductor packagers 3 on the lower tiers are different in height from a principal surface of the board 1 and alternately arranged on a first principal surface of the board 1 and a second principal surface on the side opposite to the first principal surface without contacting one another. A part of a semiconductor element 7 constituting the semiconductor package 3 on the lower tier is arranged between a semiconductor element 7 constituting the semiconductor package 2 on the upper tier and the board 1, and a part of the first spacer 4 is arranged between the semiconductor element 7 constituting the semiconductor package 3 on the lower tier and the board 1. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供高可靠性和高密度的半导体器件。解决方案：下层的半导体封装3直接安装在板1上以与其电连接，上层的半导体封装2通过第一间隔件4安装在板1上，以电连接到板，并且上层的半导体封装2和下层的半导体封装器3的高度与板1的主表面高度不同，并且交替地布置在板1的第一主表面上，并且与第一主表面相反的一侧第一主表面没有彼此接触。构成下层的半导体封装3的半导体元件7的一部分配置在构成上层的半导体封装2的半导体元件7和基板1之间，第一间隔物4的一部分配置在半导体元件7构成下层的半导体封装3和板1.版权所有（C）2009，JPO＆INPIT

7. 发明专利

JPH06131354A PROCESS CONTROL DATABASE STRUCTURE 失效
公开(公告)号：JPH06131354A
公开(公告)日：1994-05-13
申请号：JP487892
申请日：1992-01-14
申请人： HITACHI LTD , AKITA DENSHI KK
发明人： SASAKI SATORU , SAKAKI NOBORU , KUSANAGI YOSHITOMO , YAMAGAMI YUKIHIRO , ONO TOSHIAKI , KIKUCHI KATSUHIKO
IPC分类号： G06F12/00 , B65G61/00 , G05B19/418 , G06Q50/00 , G06Q50/04 , G06F15/21
摘要： PURPOSE:To save the labor and to accelerate the operating speed by providing a measurement data file and a check result file independently of each other and then inputting and retrieving the measurement data and the calculation result of the statistic value to those two files. CONSTITUTION:This structure is provided with a check item MDS(master data set) 1 where the check item information, a measurement data VDS(variable data set) 2 where the measurement data information is registered, a check result VDS 3 where the calculation result of the statistic value is registered, a measurement data date MDS 4 where the date of measurement is registered, a check date MDS 5 where the date of check is registered, a product name MDS 9 where the name information on the products, etc., are registered, a product name/product name group VDS 10 where the information on the mutual relations among the products are registered, a product name group MDS 11 where the product name group information are registered, an equipment MDS 6 where the information on the equipment names, etc., are registered, an equipment/equipment group VDS 7 where the information on the mutual relations among the equipments are registered, and an equipment group MDS 8 where the equipment group information are registered. The same linkages of each file are connected to each other.

8. 发明专利

JPS60183110A HEATING APPARATUS 失效
公开(公告)号：JPS60183110A
公开(公告)日：1985-09-18
申请号：JP3856484
申请日：1984-03-02
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD , AKITA DENSHI KK
发明人： ITOU FUJIO , NAGASHIMA NAOYUKI , KUSANAGI YOSHITOMO
IPC分类号： B29B13/08
摘要： PURPOSE:To control heating according to the desired temperature distribution by a method wherein high frequency heating quantity is designed to be controlled in each section of an electrode, the temperature distribution of each heated substance is detected and heating quantity is controlled in compliance with this distribution. CONSTITUTION:When tablets 10 are heated, infrared rays are irradiated from each section of the tablet 10 in compliance with the temperature and detected by sensors 9A...9C. Actual temperature distribution data of the heated tablets 10 are obtained on basis of this detection and these temperature distribution data are inputted to a controller 8. The controller 8 compares these actual temperature distribution data with the ideal temperature distribution data and control command signals are issued according to the difference between both data to control high frequency heating quantity to each section of the tablet 10.

9. 发明专利

JP2005072523A Semiconductor device and manufacturing method therefor 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005072523A
公开(公告)日：2005-03-17
申请号：JP2003303974
申请日：2003-08-28
申请人： Akita Denshi Systems:Kk , Hitachi Ltd , 株式会社アキタ電子システムズ , 株式会社日立製作所
发明人： KAGAYA YUTAKA , KUSANAGI YOSHITOMO , KIKUCHI TAKAYA , HATAZAWA AKIHIKO
IPC分类号： H01L25/18 , H01L23/31 , H01L23/495 , H01L23/538 , H01L25/10 , H01L25/11
CPC分类号： H01L23/3128 , H01L23/49572 , H01L23/5382 , H01L24/50 , H01L25/105 , H01L2225/1023 , H01L2225/1058 , H01L2924/12042 , H01L2924/15311 , H01L2924/15331 , H01L2924/3511 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To cope with the increase in the number of signals by standardizing a substrate which is subjected to lamination packaging of a semiconductor chip.
SOLUTION: In a semiconductor device wherein a plurality of substrates with a semiconductor chip mounted are laminated, one end of a lead formed in the substrate is connected to a semiconductor chip and the other end thereof is a connection terminal of the substrate. At least a part of the lead is branched to a plurality near a connection terminal, and the branched leads are different connection terminals. The manufacturing method has a process for carrying out piece assembly for mounting a semiconductor chip on the substrate, a process for selecting a non-defective item with the semiconductor chip mounted on the substrate, a process for performing discrete dicing treatment for the substrate of each layer, while keeping conduction of a prescribed lead from the branched lead and a process for laminating and packaging the discrete substrate in a specified order. According to this constitution, it is possible to standardize a substrate of the same pattern and to switch many signals, since it has enough space.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：通过对经过半导体芯片的层叠封装的基板进行标准化来应对信号数量的增加。解决方案：在其中安装有半导体芯片的多个衬底的半导体器件中，形成在衬底中的引线的一端连接到半导体芯片，并且其另一端是衬底的连接端子。引线的至少一部分在连接端子附近分支为多个，分支引线是不同的连接端子。该制造方法具有进行用于将半导体芯片安装在基板上的零件组装的处理，安装在基板上的半导体芯片选择无缺陷项目的处理，对各基板进行离散切割处理的工序同时保持规定的铅从分支引线的导通以及以特定顺序层叠和封装分立的衬底的工艺。根据该结构，由于具有足够的空间，因此可以使相同图案的基板标准化并切换许多信号。版权所有（C）2005，JPO＆NCIPI

10. 发明专利

JPS63199452A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS63199452A
公开(公告)日：1988-08-17
申请号：JP3146987
申请日：1987-02-16
申请人： HITACHI LTD , AKITA DENSHI KK
发明人： KUSANAGI YOSHITOMO , NAKAI TAKAFUMI
IPC分类号： H01L23/28 , H01L23/50
摘要： PURPOSE:To improve the electrical reliability of a semiconductor device by forming a support section supporting a bonding wire at an end section on the side, to which the bonding wire is connected, in a lead. CONSTITUTION:Support sections 1A supporting bonding wires 5 are shaped at end sections on the sides, to which the bonding wires 5 are connected, in leads 1 for a semiconductor device. The end section 1A on the bonding wire 5 side is directed upward so that an upper section, the extending direction of the bonding wire 5, is brought near to the surface, on which the bonding wire 5 is connected, in the lead 1 vertically as much as possible, and the end section 1A of the lead 1 functions as the support section for lengthening the shortest distanc (l) between the bonding wire 5 and a semiconductor chip 4 as much as possible. Accordingly, the sag of the bonding wire 5 is prevented, and the distance (l) between the bonding wire and the semiconductor chip 4 is lengthened, thus obviating the short circuit of the semiconductor chip 4 and the bonding wire 5.

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