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1. 发明专利

JP2001028480A MANUFACTURING SYSTEM OF THICK FILM/THIN FILM HYBRID MULTILAYER WIRING BOARD AND ELECTRON BEAM LITHOGRAPHY SYSTEM 失效
公开(公告)号：JP2001028480A
公开(公告)日：2001-01-30
申请号：JP2000152731
申请日：2000-05-19
申请人： HITACHI LTD
发明人： SAITO NORIO , TODOKORO HIDEO , KURODA KATSUHIRO , FUKUHARA SATORU , MATSUOKA GENYA , ARIMA HIDEO , YOKONO ATARU , INOUE TAKASHI , SHIGI HIDETAKA
IPC分类号： G21K5/04 , G03F7/20 , H01L21/027 , H01L23/12 , H05K3/10 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To prevent connection failure, and at the same time to achieve the high density of not only an upper thin-film circuit but also thick-film one by providing a matching layer that absorbs the misalignment between circuits at the interface between a thick-film wiring board and a thin-film wiring circuit formed at the upper portion and electrically connects terminals. SOLUTION: A ceramic thick-film wiring board 10 is equipped with five aluminum substrates 11, an inner-layer conductor 12 and an alignment mark 15 of a surface are printed by paste such as tungsten and molybdenum on such aluminum substrate 11, and a via part 13 is formed in the thick-film wiring board 10. On the backside of the thick-film wiring board 10, a land 14 is formed while the via part 13 being exposed from the backside is covered. Also, on the surface of the thick-film wiring board 10, a connection conductor pad 16 is formed while electric connection is made to the via part 13 being exposed from the surface. The connection conductor pad 16 can be used as a matching layer 62 for carrying out the matching connection between a conductor 22 for wiring in a thin-film wiring board 20 being formed on the pad and the via part 13.

2. 发明专利

JP2507561B2 失效
公开(公告)号：JP2507561B2
公开(公告)日：1996-06-12
申请号：JP26147188
申请日：1988-10-19
申请人： HITACHI LTD
发明人： YOKONO ATARU , TERABAYASHI TAKAO , KAYABA NOBUO , OOGURO TAKAHIRO , KIEDA SHIGEKAZU , KOBAYASHI FUMYUKI , ZUSHI TSUGIO
IPC分类号： H01L23/373 , H01L23/433 , H01L23/473 , H05K7/20

3. 发明专利

JPH03276655A MULTILAYER-INTERCONNECTION BOARD AND ITS MANUFACTURE 失效
公开(公告)号：JPH03276655A
公开(公告)日：1991-12-06
申请号：JP7349190
申请日：1990-03-26
申请人： HITACHI LTD
发明人： MATSUYAMA HARUHIKO , YOSHIMOTO MITSUO , TANAKA JUN , SHOJI FUSAJI , YOKONO ATARU , INOUE TAKASHI , YAMAZAKI TETSUYA , TANAKA MINORU , SHIGI HIDETAKA
IPC分类号： H05K3/46 , H01L21/60 , H01L23/498
摘要： PURPOSE:To prevent the taper face at the lower part of a through hole in a polyimide film from being undercut by a method wherein metal interconnection layers whose surface is stabilization-treated and organic insulating films are laminated alternately at least on one face of a ceramic substrate and a thin-film circuit layer provided with terminals, for power supply or/and signal input/output use, which are connected to an LSI is formed on the surface layer of the laminated layers. CONSTITUTION:A thick-film mullite substrate 1 is formed; its surface is sputtered and cleaned. After that, an Al interconnection layer 2 is formed; in succession, Cr films to be used as passivity films are formed continuously to form a laminated film, i.e., a stabilization-treated layer 9. A metal interconnection layer 10a is formed; it is connected to circuits on the mullite substrate 1; then, a polyimide insulating film 3a is formed. Then, a metal interconnection layer 10b formed in the same manner as the metal interconnection layer 10a is formed in a contact through-hole 7; a polyimide insulating film 3b is formed on the metal interconnection layer 10b. In addition, this operation is repeated alternately; metal interconnection layers 10c, 10d and polyimide insulating films 3c, 3d are formed. In succession, an Ni-Cu alloy film is formed continuously on the surface of the polyimide insulating film 3d in which the contact through-hole 7 has been formed; it is patterned; after that, Au is plated chemically; a layer for surface terminals 11 is formed.

4. 发明专利

JPH03272824A MOLDING METHOD OF SANDWICH STRUCTURE 失效
公开(公告)号：JPH03272824A
公开(公告)日：1991-12-04
申请号：JP28422290
申请日：1990-10-24
申请人： HITACHI LTD
发明人： GOTO MASAO , NAKAMURA SHOZO , WARATANI KENICHI , YOKONO ATARU , AOKI MASAYOSHI , SHIBATA KATSUO , NAKA REIJI
IPC分类号： B32B27/08 , B29C33/04 , B29C39/26 , B29C39/38 , B29C45/16 , B29C45/72 , B29C45/73 , B29K105/04 , B29L9/00 , B32B37/15
摘要： PURPOSE:To heighten the strength of a molded object by a method in which the temper ature of a mold is regulated by the flow of warm water through a thermostatic hole, whereby the fluidity of raw liquid is raised, and before the raw liquid is solidified by reaction and molds a molded object, the desired position to be strengthened of the molded object is cooled by the flow of cooling a medium through a cooling hole, thereby molding a skin layer thick. CONSTITUTION:A cooling hole 7 is bored at the corner part 5b of the top force 5A which molds the corner part of the recessed part of a molded object. The inner diameters and the positions of the cooling hole 7 and the hole 8 for temperature- regulation are determined by the various factors of the temperature, conducted heat amount, specific heat and heat conductivity of the resin poured in a mold cavity 4 and the material of the top force 5A etc. The mold-temperature in the time when the raw liquids of two kinds are poured into the mold cavity 4, is regulated by causing the warm water of 40-45 deg.C to flow through a thermostatic hole 8. Before the raw liquids of two kinds poured into the mold cavity 4 is solidified by reaction and molds a molded object, the cooling medium cooled to about -5 - +10 deg.C by liquid nitrogen gas or Freon gas etc. is caused to pass the cooling hole 7 and cools the raw liquid in the mold cavity 4 adjacent to the cooling hole 7, whereby the skin layer with high density and desired thickness is molded, and its strength is improved.

5. 发明专利

JPH03101193A THICK FILM/THIN FILM HYBRID MULTILAYER INTERCONNECTION BOARD 失效
公开(公告)号：JPH03101193A
公开(公告)日：1991-04-25
申请号：JP23565089
申请日：1989-09-13
申请人： HITACHI LTD
发明人： ARIMA HIDEO , YOKONO ATARU , INOUE TAKASHI , SAITO NORIO , TODOKORO HIDEO , KURODA KATSUHIRO , FUKUHARA SATORU , MATSUOKA GENYA , SHIGI HIDETAKA
IPC分类号： H05K3/46 , H01L23/12 , H05K3/06 , H05K3/10
摘要： PURPOSE:To obtain a high density and high reliability thick film/thin film hybrid-type multilayer interconnection board by a method wherein a matching layer with which the circuit terminals of a thick film interconnection board are electrically connected to the circuit terminals of a thin film interconnection board is provided. CONSTITUTION:A ceramic interconnection board 10 is composed of alumina boards 11 on which W-conductors 12 and register marks 15 are printed and which are connected to each other with through-holes 13 filled with W and has lands 14. A thin film circuit part 20 is formed on the board 10 with a matching layer 30 composed of the exposed through-holes 13 and pads 31 attached to them between and an LSI 40 is mounted. In order to form the pad 31, the position of the hole 13 on the board surface is estimated by a computer from the register marks 15 on the board 10. The relations between the estimated position and the position of the through-hole of the thin film circuit 20 which is to be connected to the through-hole 13 are calculated to obtain an imaginary curve. The conductor pad 31 having the imaginary curve as its outline is selectively formed. The thin film circuit 20 is composed of polyimide resin films 21 and copper thin films 22. With this constitution, a thick film/thin film hybrid-type multilayer interconnection board can be obtained.

6. 发明专利

JPH02109354A COOLING APPARATUS FOR SEMICONDUCTORS 失效
公开(公告)号：JPH02109354A
公开(公告)日：1990-04-23
申请号：JP26147188
申请日：1988-10-19
申请人： HITACHI LTD
发明人： YOKONO ATARU , TERABAYASHI TAKAO , KAYABA NOBUO , OGURO TAKAHIRO , KIEDA SHIGEKAZU , KOBAYASHI FUMIYUKI , ZUSHI SASUKE
IPC分类号： H01L23/373 , H01L23/433 , H01L23/473 , H05K7/20
摘要： PURPOSE:To make it possible to have excellent cooling performance by using a ceramic material which is the complex sinter of AlN and BN having a two-dimensional thermal conductivity, exhibiting a low thermal conductivity in a direction vertical to the two-dimension, and having excellent machinability such as cutting, grounding, and polishing. CONSTITUTION:A number of LSI chips 2 are mounted on a ceramic electrical wiring board 1. A heat cooling device 3 is incorporated between the chips 2 and a cooled body 4 cooled by an external cooler 5. Heat produced in these chips 2 flows through the heat transfer device 3 and the cooled body 4 in the direction of an arrow 6 and is carried out from the cooler 5. The device 3 is made up of a complex sinter of AlN and BN. A ceramic material having a two-dimensional thermal conductivity in a direction in which the heat of the LSI chips flow, exhibiting a low thermal conductivity in a direction vertical to the two-dimension, and having excellent machinability such as cutting, grounding, and polishing is used. Thus, a cooling apparatus for semiconductor chips having thermal conductivity performance according to the amount of heat produced in the LSI chips is obtained.

7. 发明专利

JPH0290593A MANUFACTURE OF MULTILAYER WIRING BOARD 失效
公开(公告)号：JPH0290593A
公开(公告)日：1990-03-30
申请号：JP24100688
申请日：1988-09-28
申请人： HITACHI LTD
发明人： YAMAZAKI TETSUYA , ISADA NAOYA , TANAKA JUN , KATAOKA FUMIO , YOKONO ATARU
IPC分类号： H05K3/46
摘要： PURPOSE:Not only to enable the correction of defects but also to eliminate steps easily by a method wherein a photosensitive insulating film is formed so as to level the steps, which is exposed to light and developed, the protruded insulating layer on a wiring layer is removed, and then an insulating layer is newly formed. CONSTITUTION:The whole face of a board is spin-coated with photopal, which is subjected to a heat treatment at a temperature of 85 deg.C for a half hour for the formation of a photosensitive insulating layer 6. In this process, the photosensitive insulating layer 6 has been formed in a recess 5 thicker than the other part. Then, the photosensitive layer 6 is exposed to light using a photomask and developed to remove the photosensitive insulating layer 6 on a wiring layer. Here, if a defect in evenness caused by the positional deviation of the mask is found, the photosensitive insulating layer can be selectively removed by ultrasonic cleaning. Next, the is thermally treated at a temperature of 200 deg.C for 30 minutes and 350 deg.C for 60 minutes in a nitrogen flow to enable the the photosensitive insulating layer 6 to become a flattened insulating layer 7. Then, an interlayer insulating layer 8 is newly formed. A process is reciprocated until a required number of layers are obtained for the formation of a multilayer wiring board.

8. 发明专利

JPH01268876A ELECTROLESS GOLD PLATING BATH AND GOLD PLATING METHOD USING THE SAME AND ELECTRONIC DEVICE PLATED WITH THE SAME 失效
公开(公告)号：JPH01268876A
公开(公告)日：1989-10-26
申请号：JP9551588
申请日：1988-04-20
申请人： HITACHI LTD
发明人： USHIO JIRO , MIYAZAWA OSAMU , TOMIZAWA AKIRA , YOKONO ATARU , ISADA NAOYA , MATSUURA NAOKO , ANDO SETSUO , OKUDAIRA HIROAKI , MORI YOSHIHARU
IPC分类号： H01L21/60 , C23C18/44 , H01L21/027 , H01L23/12 , H05K3/24
摘要： PURPOSE:To obtain an electroless gold plating bath free from cyanide ions, reduced in the amount of reducing agent used, and causing no short circuit of wire to wires minimal in wire spacing by providing an aqueous solution containing Au , a complexing agent having binding energy higher than that of hydroxide ion for the above Au , and a reducing agent. CONSTITUTION:An electroless gold plating bath consisting of an aqueous solution containing an Au source, such as gold (I) sodium dithiosulfate, the above completing agent, such as sodium thiosulfate, and the above reducing agent, such as thiourea, is prepared. In addition to having the above characteristics, this electroless gold plating bath can provide electroless gold plating free from problems in safety at the time of working and waste disposal. Further, by the above electroless gold plating, electronic devices, modules, and wiring boards capable of being loaded with parts in high density and improved in reliability of connection to parts can be obtained.

9. 发明专利

JPH0117453B2 失效
公开(公告)号：JPH0117453B2
公开(公告)日：1989-03-30
申请号：JP2930983
申请日：1983-02-25
申请人： HITACHI LTD
发明人： IIDA MAKOTO , TSUJIKU SUSUMU , GOTO MASAO , YOKONO ATARU
IPC分类号： B32B5/18 , B29C45/00 , B29K75/00 , B29K105/04 , B29L9/00 , B32B5/14 , B32B7/02

10. 发明专利

JPS63128699A LIGHT-SENSITIVE GLASS-CERAMIC MULTILAYER INTERCONNECTION BOARD 失效
公开(公告)号：JPS63128699A
公开(公告)日：1988-06-01
申请号：JP27400086
申请日：1986-11-19
申请人： HITACHI LTD
发明人： NORO TAKANOBU , TODA AKIZO , ARIMA HIDEO , YOKONO ATARU , TOZAKI HIROMI
IPC分类号： H05K3/46

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