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1. 发明专利

JPH06310081A ION IMPLANTATION DEVICE 失效
公开(公告)号：JPH06310081A
公开(公告)日：1994-11-04
申请号：JP10218093
申请日：1993-04-28
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： TAKAHAMA TAKASHI , USUI HIROO , YOSHIGAMI JIRO , NISHIDA TAKASHI
IPC分类号： H01J37/317 , H01L21/265
摘要： PURPOSE:To reduce a quantity of polluted atoms implanted into an ion implantation object sample when an ion is implanted. CONSTITUTION:A pressing angle 4 such as preventing the occurrence of a non- implantation area 6 is provided in response to a doping angle. The pressing angle 4 is not uniform, and an ion implantation object sample 1 having such a shape as a side wall surface of a clamp 3 and the ion beam advancing direction become parallel with each other in response to the doping angle 5 and the holding clamp 3 are installed.

2. 发明专利

JPS6032991B2 失效
公开(公告)号：JPS6032991B2
公开(公告)日：1985-07-31
申请号：JP14334176
申请日：1976-12-01
申请人： HITACHI LTD
发明人： WADA YASUO , USUI HIROO
IPC分类号： H01L29/78 , H01L21/283 , H01L21/316

3. 发明专利

JPS5688818A POLYCRYSTALLINE SILICON MEMBRANE AND ITS PRODUCTION 失效
公开(公告)号：JPS5688818A
公开(公告)日：1981-07-18
申请号：JP16276079
申请日：1979-12-17
申请人： HITACHI LTD
发明人： WADA YASUO , USUI HIROO , OOKURA OSAMU , MIYAO MASANOBU , TAMURA MASAO , TOKUYAMA KON
IPC分类号： C01B33/02 , C23C16/24 , H01L21/20 , H01L21/268 , H01L29/04 , H01L29/36
摘要： PURPOSE:The first layer with an impurity concentration higher than the solid solubility is formed on the second layer with an impurity concentration lower than the solid solubility to produce a low-resistivity polycrystalline silicon membrane that can be used in wiring or as a gate electrode of LSI. CONSTITUTION:The combination of thermal diffusion and leaser annealing is applied to form the first layer with an impurity concentration higher than the solid solubility on the second layer with an impurity concentration lower than the solid solubility, thus giving a polycrystalline silicon membrane with very low resistivity as a whole. The power density of the laser used is required to be less than about 1.1 J/cm . When it exceeds 1.2 J/cm , the polycrystalline silicon membrane melts to be deformed and cannot be used in wiring or as a gate electrode in a semiconductor device. On the contrary, when it becomes lower than about 0.3 J/cm , the annealing effect is scarcely observed, thus giving an undesirable result.

4. 发明专利

JPS55102227A ION IMPLANTATION 失效
公开(公告)号：JPS55102227A
公开(公告)日：1980-08-05
申请号：JP823979
申请日：1979-01-29
申请人： HITACHI LTD
发明人： WADA YASUO , USUI HIROO
IPC分类号： C23C14/48 , H01J37/317 , H01L21/265
摘要： PURPOSE:To form the impurity layers with different concentrations simultaneously by implanting molecular ions into the semiconductor substrate after providing a mask of the disred thickness on the substrate. CONSTITUTION:When BF2 ions are implanted, the peak 1 that is shallow and high concentrated and the peak 2 that is deep and low concentrated are developped. Since the depth of peak can be controlled by prestage acceleration voltage of the ion implantation device, the thickness of the surface oxide film can be selected in a wide range by the acceleration voltage. Also the concentration of the peak 2 can be controlled by the vacuum extent and the prestage acceleration voltage. Accordingly, when the ions are implanted so that only the peak 2 is formed except the peak 1, a layer with a greater resistance value can be obtained with a high precision. When the ions are implanted into the substrate through an oxide film of 30nm thickness, for example, the peak 1 can be removed completely, the resistance of diffusion layer is widely controlled by using a mask the film thickness of which is selectively changed and by selecting the quantity of implanted ions, the desired layer can be formed with a high precision. In this way, the resistance layers of different values from each other can be obtained at one time by using molecular ions as implanted ions.

5. 发明专利

JPH06349918A METHOD OF EVALUATING SEMICONDUCTOR 失效
公开(公告)号：JPH06349918A
公开(公告)日：1994-12-22
申请号：JP14032893
申请日：1993-06-11
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： TAKAHAMA TAKASHI , OYU SHIZUNORI , USUI HIROO , YOSHIGAMI JIRO
IPC分类号： H01L21/66
摘要： PURPOSE:To enable the resistance of an impurity introduced layer to be measured even if a punch-through phenomenon is generated by a probe in the impurity introduced layer by a method wherein a specimen whose carrier density is 1/10 as low as or less than the maximum carrier density of the impurity introduced layer and which is deeper than the impurity introduced layer is used. CONSTITUTION:The resistance of a veery shallow impurity introduced layer 1 formed on the surface region of a semiconductor substrate is measured through a two-probe method or a four-probe method 6. That is, a region 2 has a carrier density 1/10 as low as or less than the maximum carrier density of the impurity introduced layer 1, is of the same conductivity type as the impurity introduced layer 1, and deeper than the impurity introduced layer 1, and a specimen which is possessed of the region 2 concerned in a semiconductor substrate of conductivity type different from that of the impurity introduced layer 1 is used to make a measurement. By this setup, when measurement is conducted through a four- probe method or a two-probe method, the resistance of the impurity-introduce layer 1 can be measured even if a punch-through phenomenon is generated by a probe in the impurity-introduced layer 1.

6. 发明专利

JPH0684494A ION IMPLANTER 失效
公开(公告)号：JPH0684494A
公开(公告)日：1994-03-25
申请号：JP23334792
申请日：1992-09-01
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： TAKAHAMA TAKASHI , ITOGA TOSHIHIKO , USUI HIROO , HIRAIWA ATSUSHI
IPC分类号： H01J37/317 , H01L21/265
摘要： PURPOSE:To decrease the amount of contaminating atoms implanted in a sample for ion implantation by engraving more than one groove on a side wall facing the position of a clamp at which the clamp holds the sample for ion implantation. CONSTITUTION:A sample 2 for ion implantation is disposed on a platen 3 via an O-ring 4 and is held by a clamp 1. Thereafter, more than one groove is engraved in advance on a side wall facing the position of the clamp 1 at which it holds the sample for ion implantation. Next, an ion beam is introduced into the device so that ions are implanted in the sample 2 for ion implantation. Since the surface area of the clamp 1 which is exposed to the ion beam is reduced by formation of the grooves in the surface of the clamp 1, the amount of contaminating atoms from the clamp 1 sputtered by the ion beam is decreased, and the amount of contaminating atoms implanted in the sample 2 for ion implantation can be decreased.

7. 发明专利

JPH03266425A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH03266425A
公开(公告)日：1991-11-27
申请号：JP6416690
申请日：1990-03-16
申请人： HITACHI LTD
发明人： OYU SHIZUNORI , USUI HIROO , ITOGA TOSHIHIKO , HIRAIWA ATSUSHI
IPC分类号： H01L21/265
摘要： PURPOSE:To enable a shallow junction subject to low junction leakage current to be formed by a method wherein arsenic within a specific concentration range is contained in a high concentration boron layer formed on the main surface of a semiconductor substrate. CONSTITUTION:An arsenic contained layer 6 within a concentration range of 1X10 /cm -1X10 /cm is formed in a high concentration boron led-in layer in the junction regions restricted by an insulating film 2 for element isolation and a gate electrode 4 on a gate insulating film 3 formed on the surface of a semiconductor substrate 1. That is, this arsenic containing layer 6 within the concentration range can restrain the boron diffusion due to the heat treatment after the implantation of the film 6, thereby enabling a shallow junction to be formed. Furthermore, the effect can not be brought about within the concentration range not exceeding the values while the activity concentration of boron is to be affected within the concentration range exceeding the values. Through these procedures, a shallow junction subject to low junction leakage current can be formed.

8. 发明专利

JPS61214567A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS61214567A
公开(公告)日：1986-09-24
申请号：JP5441785
申请日：1985-03-20
申请人： HITACHI LTD
发明人： UEHARA KEIJIRO , USUI HIROO
IPC分类号： H01L29/73 , H01L21/331 , H01L29/72 , H01L29/732
摘要： PURPOSE:To enable the shallowing of a base layer, by reducing the amount of implanted base impurities by utilizing the characteristic of a self-aligning transistor. CONSTITUTION:An oxide film 12, a silicon nitride film 13 and a polycrystalline Si layer 14 are connected in superposition on the surface of an Si substrate 11, and B is diffused in high concentration into the layer 14. Next, an oxide film 15 and a silicon nitride film 16 are formed on the surface of the layer 14. The films 16-14 in a region in which an emitter is to be formed are removed. An oxide film 17 is formed on the lateral side of the film 14. Then, base impurities in an amount of 4X10 cm or less are implanted to form a base layer 18. A polycrystalline Si layer 19 is connected thereafter, and photoetching is applied by using a pattern larger than an emitter mask. The films 15-17 are removed. Then, the exposed film 12 is removed. The layer 19 in the emitter region is removed. When the exposed film 12 is removed, a base contact region 2 can be formed. A polycrystalline Si layer 20 is connected thereafter, and when heat treatment is applied thereto, B is diffused from the layer 14 into the layer 20. After B is diffused in the lateral direction, the layer in which B is not contained is subjected to etching. Then, an emitter layer 1 is formed.

9. 发明专利

JPS5947453B2 JPS5947453B2 - 失效
标题翻译：空值
公开(公告)号：JPS5947453B2
公开(公告)日：1984-11-19
申请号：JP3616177
申请日：1977-04-01
申请人： Hitachi Ltd
发明人： WADA YASUO , USUI HIROO
IPC分类号： H01L27/00 , H01L21/02 , H01L21/20 , H01L21/268 , H01L21/331 , H01L21/84 , H01L21/86 , H01L27/12 , H01L29/70 , H01L29/73 , H01L29/78 , H01L29/786 , H01L31/04
CPC分类号： Y02E10/50

10. 发明专利

JPS53122361A MANUFACTURE FOR SINGLE CRYSTAL SILICON THIN FILM 失效
公开(公告)号：JPS53122361A
公开(公告)日：1978-10-25
申请号：JP3616177
申请日：1977-04-01
申请人： HITACHI LTD
发明人： WADA YASUO , USUI HIROO
IPC分类号： H01L27/00 , H01L21/02 , H01L21/20 , H01L21/268 , H01L21/331 , H01L21/84 , H01L21/86 , H01L27/12 , H01L29/70 , H01L29/73 , H01L29/78 , H01L29/786 , H01L31/04
摘要： PURPOSE:To manufacture thin film of single crystal silicon by doping the impurity and annealing it, through deposit of amorphous or polycrystal silicon on the amorphous substrate.

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