专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JPH025422A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH025422A
公开(公告)日：1990-01-10
申请号：JP15470688
申请日：1988-06-24
申请人： HITACHI LTD
发明人： KATO HISAYUKI , OKAWA AKIRA , SASAKI KATSUTO
IPC分类号： H01L21/3205 , H01L21/28 , H01L23/52 , H01L29/43 , H01L29/49 , H01L29/78
摘要： PURPOSE:To reduce the film stress of a silicide and to prevent the silicide and an impurity in polysilicon from diffusing each other by a low melting point metal layer by interposing the low melting point metal layer between the layers of the silicide for forming a polyside and the polysilicon. CONSTITUTION:An electrode wiring structure in which a low melting point metal layer 21 is interposed between layers of silicide 22 for forming a polyside electrode wiring and polysilicon 20 is provided. Accordingly, a gate electrode 3 and a word line WL are reduced at the film stress of a polysilicon film 20 since the layer 21 partly melted in case of heat treating is operated as buffer material. The film 21 interposed between the films 20 and 22 is operated as a barrier layer to prevent impurities (P, As or B) introduced to the film 20 and impurities (F, Cl) due to unreacted gas mixed in the film 22 from diffusing each other.

2. 发明专利

JPS63126247A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS63126247A
公开(公告)日：1988-05-30
申请号：JP27184186
申请日：1986-11-17
申请人： HITACHI LTD
发明人： KOJIMA MASAYUKI , KOIKE ATSUYOSHI , SASAKI KATSUTO , IKEDA SHUJI
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/3205
摘要： PURPOSE:To decrease overhang of an insulation layer formed on a first interconnection layer and to prevent short circuit between first and second interconnection layers, by performing both the isotropic and anisotropic etchings for providing the first interconnection layer with blunt edges. CONSTITUTION:An insulation layer 2 and a conducting layer 3B providing a first interconnection layer are formed on the whole surface of a substrate 1. The substrate masked with a mask 6 is subjected to isotropic etching and subsequently to anisotropic ethcing for forming a first interconnection layer 3 having blunt edges 3A. After the mask 6 is removed, an insulation layer 4 is formed thereon. The blunt edges of the first interconnection layer 3 prevent the insulation layer 4 from being overhung in the sections corresponding to the edges 3A. After that, a second interconnection layer 5 is formed on the insulation layer 4. In this manner, the insulation layer 4 can be formed without overhang and, therefore, short circuit between the interconnections 3 and 5 which would be caused if any overhang is present can be prevented effectively.

3. 发明专利

JPS6345853A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS6345853A
公开(公告)日：1988-02-26
申请号：JP18852586
申请日：1986-08-13
申请人： HITACHI VLSI ENG , HITACHI LTD
发明人： MATSUDA NOZOMI , SASAKI KATSUTO
IPC分类号： G11C11/41 , H01L21/8244 , H01L27/11
摘要： PURPOSE:To weaken the parasitic MOS effect by mitigating the field concentration on the sides of semiconductor films by a method wherein sidewalls composed of insulator are provided on the sides of true semiconductor films composing high resistant resistors while the sides of said semiconductor films are inclined. CONSTITUTION:Interconnection layers 13 comprising n type polycrystalline Si film and high resistant polycrystalline Si resistors R1, R2 comprising true polycrystalline Si films connected to the interconnection layers 13 are provided on an MOSFET through the intermediary of an interlayer insulating film 12. Sidewalls 15 composed of insulator such as SiO2 are provided on the sides of said high resistant polycrystalline Si resistors R1, R2 and interconnection layer 13. Through these procedures, the distance between bit lines BL and the sides of said resistors R1, R2 is extended by the thickness of sidewalls 15. Resultantly, the electric fields generated on the sides of resistors R1, R2 can be attenuated by the bit lines BL so that parasitic MOS effect given by the bit lines BL, another interlayer insulating film 16 and the resistors R1, R2 may be weakened.

4. 发明专利

JPS6246556A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPS6246556A
公开(公告)日：1987-02-28
申请号：JP18571085
申请日：1985-08-26
申请人： HITACHI LTD
发明人： SASAKI KATSUTO , MEGURO SATOSHI
IPC分类号： H01L21/8246 , H01L27/10 , H01L27/112 , H01L29/78
摘要： PURPOSE:To stabilize the threshold voltage of a memory cell, and to improve the reliability by information writing by equalizing an impurity ion-implanted into a channel section for the memory cell. CONSTITUTION:A word line extended so that a plane shape thereof is zigzagged, a gate electrode 5 is shaped onto a gate insulating film 4 by a material having small crystal grains such as molybdenum silicide. An N-type impurity such as As or P is introduced to a P-type well 2 through a self-alignment method using the gate electrodes 5 to form N-type source-drain regions 6 in the P-type well 2. An inter-layer insulating film 7 consisting of PSG, etc. is applied on the whole surface, contact holes 8 are each bored onto the source-drain regions 6, and a plurality of aluminum wirings as data lines 9 are extended in parallel in the direction crossing with the gate electrodes 5.

5. 发明专利

JPS61218164A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS61218164A
公开(公告)日：1986-09-27
申请号：JP5836085
申请日：1985-03-25
申请人： HITACHI LTD
发明人： IKEDA SHUJI , SASAKI KATSUTO , YAMAMOTO AKIRA
IPC分类号： H01L21/8238 , H01L21/8234 , H01L27/02 , H01L27/088 , H01L27/092 , H01L29/78
摘要： PURPOSE:To improve the electrostatic damage withstand strength in an integrated circuit device having MISFET of LDD structure by employing a MISFET having no LDD on a source or drain region connected with an external terminal. CONSTITUTION:N-channel MISFETs Qn1, Qn2 for forming an output circuit 1 are mainly formed of a well region 2, an insulating film 5, a conductive layer 6 and a pair of semiconductor regions 14. The regions 14 to become the source or drain region of the FETs Qn1, Qn2 are connected with an output signal external terminal BP. The FETs Qn1, Qn2 do not employ LDD structure to enhance the electrostatic damage withstand strength. The circuit except the output circuit, i.e., n-channel MISFET Qn3 for forming an internal circuit employs the LDD structure, and is mainly formed of a well region 2, an insulating film 5, a conductive layer 6, a pair of semiconductor regions 9 and an LDD 7.

6. 发明专利

JPH0897289A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH0897289A
公开(公告)日：1996-04-12
申请号：JP26118195
申请日：1995-10-09
申请人： HITACHI LTD
发明人： TANIGAKI YUKIO , TAKAMATSU AKIRA , IKEDA SHUJI , SASAKI KATSUTO , YAMAMOTO AKIRA , KOIKE ATSUYOSHI , MORIBE SHUNJI
IPC分类号： H01L21/768 , H01L21/8244 , H01L27/11
摘要： PURPOSE: To decrease connection resistance of a conductive layer by lowering impurity concentration in the first conductive layer of the first connection part, among the first conductive layer and the multiple second conductive layers connecting to that, than that of the other second connection part. CONSTITUTION: On the main face of a semiconductor substrate 1, the first conductive layer containing a silicide layer is formed, so that, at a contact part of the surface of the first conductive layer, a protection film which prevents impurity from being introduced is formed. Then, into a part in the main face of the semiconductor substrate 1 where no first conductive layer its formed, the impurity is introduced by As ion implanting. Then, the protection film an the contact part is removed so that the first conductive layer is exposed. To the exposed first conductive layer, the second conductive layer consisting of a conductive material different from the first conductive layer is connected. Thus, a resistance value of the connection part between the first conductive layer and the third conductive layer, consisting of a polycrystalline silicon layer, which is arranged adjoining to the connection part between the first and second conductive layers, is lowered.

7. 发明专利

JPH01304768A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH01304768A
公开(公告)日：1989-12-08
申请号：JP13609888
申请日：1988-06-02
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SAIKOU YASUHIKO , SASAKI KATSUTO , KURODA KENICHI
IPC分类号： H01L27/04 , H01L21/314 , H01L21/316 , H01L21/324 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
摘要： PURPOSE:To prevent aging variation of a threshold voltage of an MISFET by providing a hydrogen ion absorption film which absorbs hydrogen ion emitted from a silicon oxide film between the MISFET and the silicon oxide film. CONSTITUTION:A memory cell of DRAM is provided with a hydrogen ion absorption film 17A at a formation region of p-channel MISFET Qp. The hydrogen ion absorption film 17A is provided to an upper part of an interlayer insulating film 8 to cover a channel formation region 3 and a source regions 10, 13 thereabout. The hydrogen ion absorption film 17A is formed by a material such as a polycrystalline silicon film or a combination film mainly composed thereof. Therefore, trapping of hydrogen ion into the channel formation region 3 or a silicon substrate thereabout can be reduced, resulting in reduction of aging variation of threshold voltage of p-channel MISFET Qp.

8. 发明专利

JPS63136647A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS63136647A
公开(公告)日：1988-06-08
申请号：JP28173586
申请日：1986-11-28
申请人： HITACHI LTD
发明人： SUGIMOTO ARITOSHI , SASAKI KATSUTO
IPC分类号： H01L21/3213
摘要： PURPOSE:To prevent a crevasse due to a mask misalignment in a manufacturing step from occurring, an electromigration or disconnection of an interconnection from occurring by forming a first layer interconnection on the top of a first layer insulator having an etching stopper layer on a front surface, etching a second insulating layer to form a connecting hole, and forming a second layer interconnection connected to the first layer wiring through the hole. CONSTITUTION:A second layer interconnection 6 is formed on the top of a first layer insulating layer 4 having an etching stopper layer 4B on the front surface, and a second layer insulating layer 7 is formed on the top of the wiring 6. The layer 7 is etched to form a connecting hole 8. Thus, if the interconnection 6 and the hole 8 are displaced at the mask alignment, the etching of the layer 7 can be controlled by the layer 4B. Accordingly, it can prevent a crevasse from being formed at the layer 4 in the hole 8. Since the layer 4B is formed to prevent the crevasse, the electric reliability of a semiconductor integrated circuit device having a multilayer interconnection structure can be improved.

9. 发明专利

JPS6281042A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS6281042A
公开(公告)日：1987-04-14
申请号：JP22000185
申请日：1985-10-04
申请人： HITACHI LTD
发明人： TANIGAKI YUKIO , TAKAMATSU AKIRA , IKEDA SHUJI , SASAKI KATSUTO , YAMAMOTO AKIRA , KOIKE ATSUYOSHI , MORIBE SHUNJI
IPC分类号： H01L21/8234 , H01L21/3205 , H01L21/768 , H01L21/8244 , H01L27/08 , H01L27/088 , H01L27/10 , H01L27/11
摘要： PURPOSE:To reduce the connection resistance of conductive layers by a method wherein, of the connecting parts of the first layer and the second multiple conductive layers connecting to the former, the impurity concentration in the first conductive layer of the first connecting part of lowered than that is the remaining first conductive layer of the second connecting part. CONSTITUTION:A dual layered film comprising a polycrystalline silicon layer 5A and a silicide layer 5B is formed on the overall surface of semiconductor substrate 1 and then the overall surface of silicide layer 5B is ion-implanted with phosphorus. The silicide layer 5B and the polycrystalline silicon layer 5A below the former 5B are patterned by etching process. A resist mask used for the etching process is left as it is without removing even after the etching process. First, another resist mask for ion-implantation to form an n type semiconductor region 7 to be a source.drain region of n channel MISFET is formed. Second, the semiconductor substrate 1 is ion-implanted with arsenic to form the n type semiconductor region 7. Through these procedures, two times of ion-implantation can be performed to form the source.drain region of n channel MISFET so that a part of silicide layer 5B connecting to an aluminum layer may be implanted with arsenic at low concentration.

10. 发明专利

JPS6265360A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS6265360A
公开(公告)日：1987-03-24
申请号：JP20422085
申请日：1985-09-18
申请人： HITACHI LTD
发明人： IKEDA SHUJI , SASAKI KATSUTO , MOTOYOSHI MAKOTO
IPC分类号： H01L27/088 , H01L21/8234 , H01L27/02 , H01L27/06 , H01L29/78
摘要： PURPOSE:To prevent a semiconductor element from breakdown due to excess electric energy by a method wherein a the excess electric energy is discharged through the bottom of a semiconductor region and the concentration is reduced of the current at the time of discharge. CONSTITUTION:Among a plurality of elements constituting an input or output buffer or the like in a region X, a MISFET in direct connection with a bonding pad 9, for example a protecting MISFET in an input protecting circuit, is provided. The MISFET in the region X is built on a p -type semiconductor region 11. Impurity concentration n and depth of the semiconductor region 11 is optimized so that the punch-through withstand voltage between the n-type semiconductor region 4 and a semiconductor substrate 1 is controlled and adjusted to be lower than that in a junction on the side of the semiconductor region 4. In a device designed as such, a surge current coming in at a bonding pad 9 is discharged to the semiconductor substrate 1 through the bottom of the semiconductor region 4, which eliminates surge current concentration. The n-type semiconductor region 4 is protected at its junction from breakdown attributable to excess electric energy.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式