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1. 发明专利

JPH07202017A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH07202017A
公开(公告)日：1995-08-04
申请号：JP33651993
申请日：1993-12-28
申请人： HITACHI LTD , HITACHI INSTRUMENTS ENG , HITACHI HOKKAI SEMICONDUCTOR , HITACHI VLSI ENG
发明人： UCHIYAMA HIROYUKI , KANEKO YOSHIYUKI , SOEDA KOKI , FUJIOKA YASUHIDE , MATSUDA NOZOMI , SAWAMURA MOTOKO
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
摘要： PURPOSE:To improve the level of integration of a device provided with a memory cell constituted of a series circuit of an MISFET for selecting memory cells and a capacitance element for storing data, by constituting the capacitance element on the gate electrode of the MISFET. CONSTITUTION:A memory cell M is constituted of an MISFET Q for selecting memory cells and a capacitance element C for storing data. A plurality of the memory cells are arranged in the row direction where word lines WL stretch and in the column direction where data lines DL stretch, and a memory cell array is constituted. One side semiconductor region 10 of the MISFET Q for selecting memory cells is connected with the data lines DL, and the other semiconductor region 10 is connected with the one side electrode (storage electrode 8A) of the capacitance element C for storing data. A gate electrode 4A is connected with the word lines WL. The other electrode (a common plate electrode 6A) is connected with a fixed potential, e.g. 1/2 Vcc fixed potential, and the level of integration of a semiconductor integrated circuit device can be increased.

2. 发明专利

JPS6329575A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPS6329575A
公开(公告)日：1988-02-08
申请号：JP17165286
申请日：1986-07-23
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUZUKI NORIO , MEGURO SATOSHI , IKEDA SHUJI , MATSUDA NOZOMI
IPC分类号： G11C11/412 , H01L21/8244 , H01L27/11 , H01L29/78
摘要： PURPOSE:To improve the degree of integration of the title device and to contrive both prevention in generation of a soft error and reduction in the area of a cell by a method wherein the source and the drain regions of an MISFET are formed on the first semiconductor region which is self-matchingly formed using a mask having the size in channel length direction smaller than a gate electrode, the second high impurity region of the conductivity type opposite to that of the first region is formed along the first region and the third high impurity region of the conductivity type opposite to that of the first region is formed under the second region and the channel region. CONSTITUTION: The low impurity density semiconductor region 8A and the high density region 8B on the main surface part of an MISFET Qd, to be used for driving, constitute the source and drain regions of double drain structure. These regions 8A and 8B are constituted in a self-matching manner to an impurity introducing mask 22 using the mask 22 having the size in channel length direction smaller than a gate electrode 9. Also, the channel length of the MISFET Qs to be used for transfer is formed in the minimum working size. On the other hand, the size in channel length direction of the gate electrode 9 of the MISFET Wd for driving is formed as large as possible provided that the electrode 9 does not come in contact with the other electrode 9. Through these procedures, the area of memory cell M can be reduced, and the degree of integration of the SRAM can also be improved.

3. 发明专利

JPH06267977A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH06267977A
公开(公告)日：1994-09-22
申请号：JP5167493
申请日：1993-03-12
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： ARIGA SEIICHI , MATSUDA NOZOMI , YOSHIDA SEIJI , MORI CHIEMI , TOYOKAWA SHIGEYA , IWANAGA TAIJI , KUNIMOTO YUKINORI
IPC分类号： H01L21/265 , H01L21/28 , H01L21/336 , H01L21/8244 , H01L27/11 , H01L29/78 , H01L29/784
摘要： PURPOSE:To improve an electric characteristic of a MISFET by reducing resistance of a diffusion layer directly under a contact hole and a contact resistance between this diffusion layer and a conductive layer. CONSTITUTION:Prior to a process of forming a contact hole by opening an insulating film 3 between the gates 2, 2 of a pair of a MISFET formed on a semiconductor substrate 1, ion implantation is performed on the semiconductor substrate 1 in the contact hole forming region from the direction to be slanting being seen from a section of a semiconductor substrate 1 along the extending direction of the gate electrode 2 and to be vertical being seen from the section of the semiconductor substrate 1 along the direction orthogonal to the extending direction of the gate electrode 2. Next, after the contact hole is formed, a conductive layer is formed on the upper part of the MISFET in order to electrically connect the conductive layer to a diffusion layer 4 directly under the contact hole through the contact hole.

4. 发明专利

JPH06252169A SEMICONDUCTOR DEVICE AND ITS MANUFACTURING THEREOF 失效
公开(公告)号：JPH06252169A
公开(公告)日：1994-09-09
申请号：JP3186193
申请日：1993-02-22
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： YOSHIDA SEIJI , TOYOKAWA SHIGEYA , MATSUDA NOZOMI , ARIGA SEIICHI , MORI CHIEMI , IWANAGA TAIJI
IPC分类号： H01L29/78 , H01L21/336 , H01L29/786 , H01L29/784
摘要： PURPOSE:To make it possible to form a channel region, a source region, and a drain region with self-alignment without using a host mask by depositing a semiconductor layer on a gate electrode and on a main surface through an insulation film and etching back the semiconductor layer until the gate insulation film is exposed. CONSTITUTION:In a semiconductor device of a lower section gate structure where a gate electrode 13 is formed on the insulating main surface 12, the gate electrode 13 is formed on the insulating main surface 12 of a substrate 11, and the gate electrode 13 is covered with a gate insulation film 14 to form first semiconductor layer 15 on the upper gate electrode 13 and on the upper section of the main surface 12 through the insulation film 14. Further, the first semiconductor layer 15 on the gate insulation film 14 positioned on the upper section of the gate electrode 13 is removed to form a source region 15a and a drain 15b are formed on both ends of the gate electrode 13. Furthermore, a second semiconductor layer 16 to serve as an opposite conductivity type channel region with respect to the first semiconductor layer 15 is formed on the insulation film 14 on the upper section of the gate electrode 14 and on the first semiconductor layer 15.

5. 发明专利

JPH088348A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND FABRICATION THEREOF 失效
公开(公告)号：JPH088348A
公开(公告)日：1996-01-12
申请号：JP13707494
申请日：1994-06-20
申请人： HITACHI LTD , HITACHI HOKKAI SEMICONDUCTOR , HITACHI INSTRUMENTS ENG , HITACHI VLSI ENG
发明人： FUJIOKA YASUHIDE , UCHIYAMA HIROYUKI , KANEKO YOSHIYUKI , SOEDA KOKI , MATSUDA NOZOMI , SAWAMURA MOTOKO
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L21/8246 , H01L27/10 , H01L27/105 , H01L27/108
摘要： PURPOSE:To enhance reliability of a DRAM, along the fabrication yield thereof, in which capacitive insulating film of a capacitive element (capacitor) for storing information is composed of a ferroelectric trim. CONSTITUTION:A polisilicon film 13 filling a contact hole 12 reaching one semiconductor region 7 of an MTSFET Qt for selecting the memory cell constitutes a storage electrode 13. The surface of the storage electrode 13 is then made flat thus depositing a PZT film 14 with low step coverage stably. Furthermore, the upper and lower layers of the PZT film 14 are provided with high melting point metal films 15, 17 in order to prevent interfacial reaction between the storage electrode or a plate electrode 16 and the PZT film 14 caused by heat treatment during the fabrication process.

6. 发明专利

JPS6345853A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS6345853A
公开(公告)日：1988-02-26
申请号：JP18852586
申请日：1986-08-13
申请人： HITACHI VLSI ENG , HITACHI LTD
发明人： MATSUDA NOZOMI , SASAKI KATSUTO
IPC分类号： G11C11/41 , H01L21/8244 , H01L27/11
摘要： PURPOSE:To weaken the parasitic MOS effect by mitigating the field concentration on the sides of semiconductor films by a method wherein sidewalls composed of insulator are provided on the sides of true semiconductor films composing high resistant resistors while the sides of said semiconductor films are inclined. CONSTITUTION:Interconnection layers 13 comprising n type polycrystalline Si film and high resistant polycrystalline Si resistors R1, R2 comprising true polycrystalline Si films connected to the interconnection layers 13 are provided on an MOSFET through the intermediary of an interlayer insulating film 12. Sidewalls 15 composed of insulator such as SiO2 are provided on the sides of said high resistant polycrystalline Si resistors R1, R2 and interconnection layer 13. Through these procedures, the distance between bit lines BL and the sides of said resistors R1, R2 is extended by the thickness of sidewalls 15. Resultantly, the electric fields generated on the sides of resistors R1, R2 can be attenuated by the bit lines BL so that parasitic MOS effect given by the bit lines BL, another interlayer insulating film 16 and the resistors R1, R2 may be weakened.

7. 发明专利

JPH02284466A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH02284466A
公开(公告)日：1990-11-21
申请号：JP10444189
申请日：1989-04-26
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MOTOYOSHI MAKOTO , SUZUKI NORIO , TAKAHASHI MASATO , MATSUDA NOZOMI
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8244 , H01L27/11
摘要： PURPOSE:To suppress the creation of a soft error without causing a disadvantage such as the degradation of a junction breakdown strength, etc., by a method wherein two storage nodes of a flip-flop circuit which holds information statically are connected to each other through a capacity element having a specific composition. CONSTITUTION:N-type channel driving MIS-FET's Q1 and Q2 are connected to resistors R1 and R2 respectively in series in a memory cell SRAM. The gate electrodes of the MIS-FET's Q1 and Q2 are connected to storage nodes N2 and N1 respectively and the nodes N1 and N2 are connected to data lines DL and DL' through selecting MIS-FET's QS1 and QS2 respectively. Further, the gate electrodes of the MIS-FET's QS1 and QS2 are connected to a word line WL. When information is written, a high potential is applied to the lines WL and DL and a low potential is applied to the line DL' and the node N1 is maintained at a high level and the node N2 is maintained at a low level. Even if alpha-rays penetrate into the memory cell and the node potential is undesirably lowered, as a capacity element Ci always tends to maintain the potential difference between its terminals constant, the inversion of the potentials of the nodes N1 and N2, i.e., a soft error, is hardly created.

8. 发明专利

JPS6329576A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS6329576A
公开(公告)日：1988-02-08
申请号：JP17165486
申请日：1986-07-23
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUZUKI NORIO , MEGURO SATOSHI , IKEDA SHUJI , MATSUDA NOZOMI
IPC分类号： H01L21/8244 , H01L27/11
摘要： PURPOSE: To reduce the occupation area of a wiring as well as to contrive improvement in the integration of an SRAM by a method wherein the wiring to be used for the reference voltage, which will be connected to the MISFET for driving of a memory cell, is formed using the conductive material having the specific resistance value smaller than that of a source or a drain region, and a conductive layer different from a gate electrode is formed. CONSTITUTION: The wiring (Vss) 15A, to be used for the reference voltage, is connected to the semiconductor region 8B of the MISFET Qd to be used for driving through a connection hole 14A. Then, the wiring 15A for the reference voltage is extended in the column direction same as the direction in which the first word line 9A is extended and provided on an interlayer film 13. Also, said wiring 15A is composed of the conductive material having the specific resistance value smaller than that of the semiconductor region 8B (or 12) such as a single layer of polycrystalline silicon film and the like same as a gate electrode 9, for example, which is the second layer of conductive layer formed in the manufacturing process. As a result, the occupation area of the wiring 15A can be reduced, and as both gate electrodes 9 of a driving MISFET Qd and the reference voltage wiring 15A can be superposed without requiring the measurements of separation between the gate electrode 9 and the wiring 15A, the area of memory cell M in row direction can also be reduced.

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