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1. 发明专利

JP2001257670A CONTENTS STORAGE DEVICE AND CONTENTS READER 失效
公开(公告)号：JP2001257670A
公开(公告)日：2001-09-21
申请号：JP2000070671
申请日：2000-03-14
申请人： HITACHI LTD
发明人： TSUNEHIRO TAKASHI , KATAYAMA KUNIHIRO , MIZUSHIMA EIGA , TSUNODA MOTOYASU , SHIRAISHI KAZUHISA , TOTSUKA TAKASHI , MANO HIROYUKI , NAKAMURA KAZUO
IPC分类号： G06F12/14 , G06F17/30 , G06F21/00 , G06F21/10 , G06F21/44 , G06F21/60 , G06F21/62 , G06K17/00 , G09C1/00 , G11B20/00 , G11B20/10 , H04L9/10 , H04N5/91 , H04N7/167 , H04N21/4335 , H04N21/4405 , G06F15/00
摘要： PROBLEM TO BE SOLVED: To deal with mass contents data while protecting the contents author. SOLUTION: License keys prepared for respective pieces of contents data are stored in a key storage device 101 which is installed apart from a hard disk device 106 for storing ciphered contents data. A key storage device 14 has the authentication function of a communication opposite party. When a reproduction device is authenticated as the communication opposite party by the function, the license key corresponding to contents data being the object of reproduction is transmitted to the reproduction device by using cipher communications. When a memory card is authenticated as the communication opposite party, the license key being the object of a request is transmitted by using cipher communications and the transmitted license key is deleted from a stored content.

2. 发明专利

JPH03137803A SYSTEM AND CIRCUIT FOR WRITE COMPENSATION OF MAGNETIC STORAGE DEVICE 失效
公开(公告)号：JPH03137803A
公开(公告)日：1991-06-12
申请号：JP27525889
申请日：1989-10-23
申请人： HITACHI LTD , HITACHI VIDEO ENG
发明人： SAIKI EISAKU , KARASAWA NORIYUKI , SUZUMURA SHINTARO , SHIRAISHI KAZUHISA , ARAI SHINICHI
IPC分类号： G11B5/09 , F02B75/02
摘要： PURPOSE:To eliminate the limitation of a correction quantity by expanding the range of write compensation optionally in units of a half or one cycle of a shift clock according to the number of stages of latches to be inserted. CONSTITUTION:Write data 5 is inputted to a data shift circuit 1 with the shift clock 6 and a correction quantity decision circuit 2 outputs '1' for a bit output corresponding to the correction quantity according to the output of the shift circuit. The output A corresponding to the correction quantity to be added is sent to an A latch 9 and the decision output is held at the fall of the clock 6. Further, some outputs of the A latch 9 are sent to a B latch 10 and held at the rise of the clock 6. The outputs of the A and B latches 9 and 10 are inputted to corresponding correction data generating latches 3 and outputted at the timing of a clock for correction generated by a delay line 4 to become corrected write pulses 8. The possible range of the write clocks for correction corresponding to the outputs of both the latches 9 and 10 is as shown by an equation I and the total correctable range of the output of the B latch 10 with half shift clock cycle delay is as shown by an equation II and becomes a 1/2 cycle wider.

3. 发明专利

JPH0391168A SYSTEM AND DEVICE FOR MAGNETIC RECORDING AND REPRODUCTION 失效
公开(公告)号：JPH0391168A
公开(公告)日：1991-04-16
申请号：JP22658989
申请日：1989-09-01
申请人： HITACHI LTD
发明人： OEDA TAKASHI , SAIKI EISAKU , KAWAMURA TETSUSHI , SHIRAISHI KAZUHISA
IPC分类号： G06F3/06 , G11B20/14
摘要： PURPOSE:To attain a small scale and high acceleration in making a system into a parallel system by sharing a write clock generation circuit and a phase locked loop circuit with plural systems of recording and reproduction circuits. CONSTITUTION:When data is recorded, encoder circuits 14a, 14b in all the recording and reproduction circuits 6a, 6b are operated according to the clock of the write clock generation circuit 15, and parallel data are recorded at the same timing with the read/write heads 1a, 1b of each of the recording and reproduction circuit 6a, 6b. When the data is reproduced, the simultaneous readout are performed with the plural read/write heads 1a, 1b. Only a single phase locked loop circuit 4 is prepared in plural systems, and only the output signal of one system of waveform arranging circuit 3a is inputted to the phase locked loop circuit 4, and the output clock 10 of the circuit is shared with the decoder circuits 5a, 5b of each system. In such a way, the small scale and the high acceleration can be attained in the making of the system into the parallel system.

4. 发明专利

JPS61199280A ACCESS CONTROL SYSTEM FOR DISK DEVICE 失效
公开(公告)号：JPS61199280A
公开(公告)日：1986-09-03
申请号：JP3873885
申请日：1985-03-01
申请人： HITACHI LTD
发明人： TOKIDA KATSUHIRO , SHIRAISHI KAZUHISA , TAKEDA KOICHI , IWAI TAKEO , HONDA HIDEICHI
IPC分类号： G11B21/08 , G11B21/10
摘要： PURPOSE:To prevent the uncontrollable run of an actuator and to suppress impact applied to a head by detecting abnormality of access by a residual signal of an objective track and a present track of a head and an access abnormality area detecting signal, and decelerating the actuator. CONSTITUTION:A present track of a head is detected by a track position detector 25, a track pass pulse generator 26 and a track address counter 27 based on servo signals from a servo head. Residual number of the present track and an objective track stored in an objective track register from a host controlling device 24 is calculated by a subtracter circuit 28, and supplied together with an area signal by a missing pattern based on the servo signal from an area detector 30, and an access abnormality signal is outputted from an access abnormality detector 29. Then, the actuator is decelerated through a target speed outputting device 31. As abnormality is detected while the head is in the data area, uncontrollable run of the actuator is prevented, and impact applied to the head is suppressed.

5. 发明专利

JPS6163966A Reading circuit 失效
标题翻译：阅读电路
公开(公告)号：JPS6163966A
公开(公告)日：1986-04-02
申请号：JP18460984
申请日：1984-09-05
申请人： Hitachi Ltd
发明人： SHIRAISHI KAZUHISA
IPC分类号： G11B5/09 , G11B20/10
CPC分类号： G11B20/10009
摘要： PURPOSE:To shorten the time needed for settle-down of a transient phenomenon that is decided by the offset voltage by reading data after actuating a switch circuit which switches the cut-off frequency of a differentiating circuit of an input stage just for a prescribed period of time when the offset voltage for input stage of a reading circuit is produced. CONSTITUTION:The data written to a floppy disk is picked up by a magnetic head 1 and amplified by a DC direct-coupled amplifier 2. The high band component of the amplified data is cut off by an LPF6 after undergoing the gain control through an AGC circuit 5. Then the data is shaped by a pulse shaping circuit 8 and read out in the form of READ DATA after undergoing the peak detection through a differentiating circuit 7. When a reading action is started after a writing action is through, it requires some settle-down time to secure a state where a reading circuit is stable and data are delivered from the circuit 8 by means of the input offset voltage of the amplifier 2 and a transient phenomenon produced by an AC coupled differentiating circuit 3. Here a switch circuit 4 is actuated for a fixed period of time to give the short to a differential signal. Thus an AC coupled differential constant is decreased. In such a way the settle- down time can be shortened.
摘要翻译：目的：缩短通过在启动将输入级的微分电路的截止频率切换到规定期间的开关电路之后读取数据的偏移电压来决定的瞬态现象所需的时间的时间，用于产生读取电路的输入级的偏移电压。构成：写入软磁盘的数据由磁头1拾取并由DC直流耦合放大器2放大。放大数据的高频分量在通过AGC进行增益控制之后被LPF6切断然后通过脉冲整形电路8对数据进行整形，并通过微分电路7进行峰值检测后以读数据的形式读出数据。当写入动作通过后开始读取动作时，需要一些稳定时间以确保读取电路稳定的状态，并且通过放大器2的输入偏移电压从电路8传送数据，以及由AC耦合差分电路3产生的瞬态现象。这里，开关电路 4被激活一段固定的时间以给出差分信号的短路。因此，AC耦合差分常数减小。以这种方式，可以缩短安定时间。

6. 发明专利

JPH0773598A TIMING SAMPLING CIRCUIT AND RECORDING AND REPRODUCING DEVICE USING THE SAME 失效
公开(公告)号：JPH0773598A
公开(公告)日：1995-03-17
申请号：JP15951593
申请日：1993-06-29
申请人： HITACHI LTD
发明人： HIRANO AKIHIKO , TAKASHI TERUMI , IWABUCHI KAZUNORI , YAMAKAWA HIDEYUKI , ISHIDA YOSHITERU , SHIRAISHI KAZUHISA , ASHIKAWA KAZUTOSHI
IPC分类号： G11B20/14 , G11B27/30 , H03L7/06 , H03L7/081 , H03L7/099 , H03L7/183 , H04L7/033
摘要： PURPOSE:To reduce an initial phase error for a clock at the time of start of phase pull-in, to lower setting values of each specific frequency of a feedback loop and to improve reliability of operation. CONSTITUTION:Clocks 106-1-106-n having different phases are supplied form a clock generating means not shown in figure, a MPX 43 selects the clock 106-1 out of them as a clock 106, it is supplied to an A/D converter not shown in figure as a sampling pulse, and its output data is supplied to a phase error quantity discriminating circuit 41 as an input data 105. The phase error quantity discriminating circuit 41 detects quantity of a phase error from the input data 105, the MPX 43 selects data in which a phase error is the minimum out of clocks 106-1 to 106-n as a clock 106 by a control signal 301 corresponding to this error. During it, a freeze circuit 42 outputs a constant phase error signal to the clock generating means, when this selection is finished, an output of a phase comparator 11 is supplied to the clock generating circuit.

7. 发明专利

JPH06290543A HDD DATA REPRODUCING CIRCUIT 失效
公开(公告)号：JPH06290543A
公开(公告)日：1994-10-18
申请号：JP7333693
申请日：1993-03-31
申请人： HITACHI LTD
发明人： IWABUCHI KAZUNORI , TAKASHI TERUMI , HIRANO AKIHIKO , YAMAKAWA HIDEYUKI , ISHIDA YOSHITERU , SHIRAISHI KAZUHISA
IPC分类号： G11B20/10 , H04L25/497
摘要： PURPOSE:To realize the high speed setting of a parameter and to simply realize the large capacity of an HDD by PRML dealing with CDR. CONSTITUTION:When the data on a recording disk 1 divided to zones for dealing with the CDR are reproduced, a parameter value read out from a parameter storage memory 14 is set to a parameter register 13 directly by a FRASH-SET circuit 12 according to the instruction by a micro processor 15. Thus, the states of a VFO center oscillation frequency, a characteristic variable filter 3 and an FIR digital filter 8 are revised, and the reproduction of the data are performed in a new operational state. Thus, a data reproducing circuit is capable of dealing with the frequency characteristic and the data transfer speed of a read waveform different at every zone at high speed, and a hard disk drive utilizing the PRML and the CDR simultaneously is materialized.

8. 发明专利

JPH03225683A POSITIONING CONTROLLER FOR HEAD 失效
公开(公告)号：JPH03225683A
公开(公告)日：1991-10-04
申请号：JP1881690
申请日：1990-01-31
申请人： HITACHI LTD
发明人： ONOYAMA KATSUMOTO , SATO MASAHIKO , YAMASHITA TADAHARU , CHUMA AKIRA , SHIRAISHI KAZUHISA
IPC分类号： G11B21/10
摘要： PURPOSE:To accurately detect servo information by automatically controlling the gain of a read amplifier when a head passes through the first area of servo information areas during seek, and afterwards fixing the gain. CONSTITUTION:A microcomputer 2 judges whether a head 5 is under seek or not, and when it is under seek, a timer is set. Then, the signal of a logical value '1' is sent out to an output line 10 and seek control is performed to the gain of a read amplifier 1. When the head 5 passes through a data area 12 at the set time of the timer, a logical value '0' of a logic signal is sent out and the gain of the read amplifier 1 is fixed. Therefore, noise to be generated at the time of switching the head is not erroneously recognized as the servo information and seek can be exactly performed onto a target track. Thus, the exact servo information can be detected.

9. 发明专利

JPH0395773A RECORDING DATA REPRODUCING DEVICE AND WINDOW FORMING CIRCUIT 失效
公开(公告)号：JPH0395773A
公开(公告)日：1991-04-22
申请号：JP23227789
申请日：1989-09-07
申请人： HITACHI LTD , HITACHI VIDEO ENG
发明人： SAIKI EISAKU , SUZUMURA SHINTARO , SHIRAISHI KAZUHISA , KOJIMA SHINICHI
IPC分类号： G11B20/14
摘要： PURPOSE:To make a window margin maximum by self-adjustment by forming multi-level windows from a window to be formed by an output from a phase synchronizing circuit, selecting the window with optimum phase difference to a data signal and decoding the data signal by using this window. CONSTITUTION:This device is provided with a phase synchronizing circuit 1, frequency divider circuit 2, delay circuit 3, window center detection circuit 4, mean calculation circuit 5 and selector 6. The delay circuit 3 delays a window 10 to be outputted from the frequency divider circuit 2 by (n) steps, is equipped with output terminals parallelly for each step 1 to (n) and outputs multi-level windows 11-1 to 11-n. Based on a select signal 13 to be outputted by the average calculation circuit 5, the selector 6 selects one of the windows 11-1 to 11-n to be outputted from the delay circuit 3 and outputs it as a window 14 to a decoder 7. By using the selected window 14, the data signal is decoded. Thus, phase deviation can be automatically adjusted so that the window margin can always be made maximum.

10. 发明专利

JPH02198007A MAGNETIC DISK DEVICE 失效
公开(公告)号：JPH02198007A
公开(公告)日：1990-08-06
申请号：JP1506289
申请日：1989-01-26
申请人： HITACHI LTD , HITACHI COMPUTER PERIPHERALS
发明人： KAMEOKA TETSUJI , TOKIDA YOSHINORI , OBATA SUMIO , SHIRAISHI KAZUHISA
IPC分类号： G11B5/09 , G11B5/596
摘要： PURPOSE:To eliminate the magnetical and electrical influences of the writing current of a data head on a servo head by simple means by controlling the writing current value of the data head in accordance with the distance from the servo head. CONSTITUTION:A write driver 3 converts write data 5 to the inversion current of the current value determined by a writing current setting circuit 4 and supplies the same to a head selecting circuit 2 at the time of data writing. The head is selected by the circuit 2 and the writing current is caused to flow. The writing current value for each of the heads set in this circuit 4 is so set as to decrease the current for the data heads nearer the servo head and to increase the current as the heads are parted from the servo head. The writing current of the magnitude corresponding to the head selected by a head select signal is transmitted to the driver 3. The magnetical and electrical influences of the writing current on the servo head is eliminated in this way by the simple means.

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