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1. 发明专利

JPS61101189A Picture recorder 失效
标题翻译：图片记录器
公开(公告)号：JPS61101189A
公开(公告)日：1986-05-20
申请号：JP22208684
申请日：1984-10-24
申请人： Hitachi Ltd
发明人： KASAHARA MASUMI , UEDA SEIICHI , UEHARA YOICHI , KONYA RYOZO
IPC分类号： H04N9/79
摘要： PURPOSE: To prevent effect of interference of a chrominance signal by providing a prescribed synchronizing relation between the sampling period and a color burst signal included in a composite picture signal in extracting a monochroic picture signal from a color composite signal.
CONSTITUTION: A digital color composite picture signal Vd of a receiver 1 is given to a bus L. An OSC section 16 consists of a PLL to generate a sampling clock fs of an A/D converter 12. The frequency of a clock fs is set sufficiently higher than the maximum frequency of a color composite picture signal Va. The OSC section uses a PLL to apply phase lock to the period of the clock fs to one over an integer of the period of the color burst signal B. The sampling circuit 21 of the picture recorder 2 samples the signal Vd by using a sampling clock fs/m having a comparatively longer period. A 1/m frequency division circuit 25 frequency-divides the frequency of the clock fs of the receiver 1 to one over m (integer) to generate a clock fs/m. Thus, the clock fs/m has always a prescribed synchronizing relation to the signal B.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：通过在彩色复合信号中提取单色图像信号，在采样周期和复合图像信号中包含的色同步信号之间提供规定的同步关系，以防止色度信号的干扰的影响。构成：将接收机1的数字彩色复合图像信号Vd提供给总线L.OSC部分16由PLL产生A / D转换器12的采样时钟fs。时钟fs的频率被设定足够高于彩色复合图像信号Va的最大频率，OSC部分使用PLL将时钟fs的周期中的相位锁定到彩色同步信号B的周期的整数之间的一个。采样电路21 图像记录器2通过使用具有较长周期的采样时钟fs / m对信号Vd进行采样。 1 / m分频电路25将接收机1的时钟fs的频率分频为m（整数），以产生时钟fs / m。因此，时钟fs / m与信号B总是具有规定的同步关系。

2. 发明专利

JP2000156048A SEMICONDUCTOR DEVICE USING JUDGMENT FEEDBACK EQUALIZER AND DIGITAL SIGNAL RECORDING AND REPRODUCING DEVICE USING IT 失效
公开(公告)号：JP2000156048A
公开(公告)日：2000-06-06
申请号：JP32772998
申请日：1998-11-18
申请人： HITACHI LTD
发明人： UMEMOTO MASUO , UEHARA YOICHI , MATSUURA TATSUJI
IPC分类号： G11B5/09 , G11B20/10 , G11B20/14 , G11B20/18
摘要： PROBLEM TO BE SOLVED: To increase further density of a magnetic disk by detecting that a different point is one bit in the prescribed block in two discrimination result groups, referring to whether total numbers of +1 of recording signals previously set are even numbers or odd numbers, and correcting this one bit. SOLUTION: Two CSE values in an eraser zone are obtained by arithmetic circuits M-10-1, M-10-2, they are compared by a comparator M-7, a less group is selected by a selector M-8 based on the compared result. As total numbers of +1 in a recording signal are set to even numbers for each prescribed block in a final result output circuit M-11, total numbers of +1s in a discriminated result are counted for each prescribed block, when they are even numbers, an output of the selector M-8 is made a final output F-out assuming that an error does not exist. When odd numbers are detected, it is judged whether they are conditions which can be corrected or not, when conditions are satisfied, they are corrected, and made the final result.

3. 发明专利

JPH11149712A MAGNETIC DISK APPARATUS AND SEMICONDUCTOR DEVICE USED FOR THE SAME 失效
公开(公告)号：JPH11149712A
公开(公告)日：1999-06-02
申请号：JP31681597
申请日：1997-11-18
申请人： HITACHI LTD
发明人： UMEMOTO MASUO , UEHARA YOICHI
IPC分类号： G11B20/10
摘要： PROBLEM TO BE SOLVED: To obtain a magnetic disk apparatus which can eliminate a signal series which is repeated in an input signal by a method wherein a pseudo random series is added to a binary input data sequence, a control signal which selects a later data series and an original data series is generated and the control signal is output as recording data. SOLUTION: Input data is input to an addition circuit 1 of modulo 2, and its output is input to a counter 3 and to a byte-unit repetitive detection circuit 4. The output of the counter 3 and that of the repetitive detection circuit 4 generate a selection control signal Cout in a judgment circuit 5. Then, when the counter 3 is at a prescribed number or lower, an original signal sequence data are selected, and, when the counter 3 is at the prescribed number or higher and when the detection circuit 4 is at the prescribed number or lower, a signal sequence to which a pseudo random sequence is added is selected as a signal sequence R-data for recording. In addition, when the counter 3 is at the prescribed number or higher and when the repetitive detection circuit 4 is at the prescribed number or higher, the original signal sequence data are selected as the signal series R-data for recording.

4. 发明专利

JPH117736A METHOD AND APPARATUS FOR DETECTING ERROR, DECODING APPARATUS, AND, RECORDING REPRODUCING APPARATUS 失效
公开(公告)号：JPH117736A
公开(公告)日：1999-01-12
申请号：JP15842297
申请日：1997-06-16
申请人： HITACHI LTD
发明人： KATAYAMA YUKARI , NISHITANI TAKUJI , NARA TAKASHI , UEHARA YOICHI , NISHINA MASATOSHI
IPC分类号： G11B20/18 , H03M13/00
摘要： PROBLEM TO BE SOLVED: To improve error correction efficiency without increasing a byte length of an ECC when RLL(run length limit coded) recording data with the ECC(error-correcting code) added thereto are reproduced. SOLUTION: A reproduction signal is subjected to input signal process (P600) and ECC run length adjustment (P506). Moreover, the signal is subjected to RLL error detection (P505). As a result, it is judged whether the signal can be an RLL code. On the occasion of an ECC error correction (P507), a position of an error code detected at the RLL error detection is used as an erasure flag. Data after the ECC error correction are subjected to RLL decoding and further to CRC(cyclic redundancy code) error detection, whereby user data are generated.

5. 发明专利

JPH1022840A DIGITAL SIGNAL DECODER AND DECODING METHOD THERFOR 失效
公开(公告)号：JPH1022840A
公开(公告)日：1998-01-23
申请号：JP16897696
申请日：1996-06-28
申请人： HITACHI LTD
发明人： NISHITANI TAKUJI , YAMAKAWA HIDEYUKI , MIYAZAWA SHOICHI , MITA SEIICHI , UEHARA YOICHI , NARA TAKASHI , HIRANO AKIHIKO
IPC分类号： G11B20/18 , G11B20/10 , H03M13/23 , H03M13/41 , H04L25/497 , H03M13/12
摘要： PROBLEM TO BE SOLVED: To attain high-speed processing and to suppress complexity in the circuit for the decoder by selecting an alive path and a branch metric for each node from a metric of each node of a stage and adding a branch metric of each node to a metric of the alive path. SOLUTION: Captions C/S 26, 28 are arithmetic units for executing comparison/selection arithmetic operations. They compare four alive metric inputs and provide outputs of alive sequence pointers SM0-SM7 and also metrics M0 -M7 of each alive path selected newly. A SEL 61 selects any branch metric among the branch metric objects outputted from a BMU, according to the alive sequence pointers SM0-SM7. The selected branch metric is added to a metric of each node. The obtained result is fed back to a corresponding state, for the succeeding arithmetic cycle.

6. 发明专利

JP2000261329A VITERBI IDENTIFYING METHOD, LEAD CHANNEL SEMICONDUCTOR DEVICE AND MAGNETIC DISK DEVICE 失效
公开(公告)号：JP2000261329A
公开(公告)日：2000-09-22
申请号：JP6116399
申请日：1999-03-09
申请人： HITACHI LTD
发明人： UMEMOTO MASUO , UEHARA YOICHI
IPC分类号： H03M13/23 , G11B20/14 , G11B20/18 , H04L1/00
摘要： PROBLEM TO BE SOLVED: To realize application with a small circuit scale by executing a processing at every two clock processing, comparing the groups of metrics whose difference of metrics is estimated to be small at first among plural metrics which are modulo-normalized and selecting the minimum metric. SOLUTION: In comparison circuits 17-1 and 17-2 for the binary code of a complement system using modulo normalization, first comparison is executed. In the case of metric P1

7. 发明专利

JPH11296992A SEMICONDUCTOR INTEGRATED CIRCUIT AND DISK ACCESS DEVICE 失效
公开(公告)号：JPH11296992A
公开(公告)日：1999-10-29
申请号：JP10164798
申请日：1998-04-14
申请人： HITACHI LTD
发明人： UEHARA YOICHI , UMEMOTO MASUO , KATO TAKATOSHI
IPC分类号： G11B20/10 , H01L21/822 , H01L27/04 , H03H15/00
摘要： PROBLEM TO BE SOLVED: To provide a signal processing semiconductor integrated circuit which detects error transmission caused by noise in a discrimination feedback equalizer, stops continuous error transmission, and is suitable to the reproduction of a high density storage disk. SOLUTION: The output of an adder 2 in a MDFE type discrimination feedback equalizer is delayed by a delay circuit 6 by the prescribed operation period, and a difference signal between a delay output and an adder output is generated by a difference signal generating circuit 7. Difference of data between before and after a tail part of an impulse responding waveform of a pre-filter 1 is comparatively small, but it becomes comparatively larger in a part in which polarity is reversed. Excluding the case in which inversion of polarity is caused by an error, an error component is hard to appear in a difference signal. Therefore, when a difference signal is larger than the prescribed threshold value in an absolute value, it can be discriminated that inversion of polarity is caused. A difference comparison discrimination control circuit 8 discriminates this, and corrects correspondent information of a feedback register 5.

8. 发明专利

JPH11243345A ENCODING METHOD AND RECORDING AND REPRODUCING DEVICE USING THE SAME 失效
公开(公告)号：JPH11243345A
公开(公告)日：1999-09-07
申请号：JP4318698
申请日：1998-02-25
申请人： HITACHI LTD
发明人： NISHITANI TAKUJI , HIRAI TATSUYA , MITA SEIICHI , NARA TAKASHI , UEHARA YOICHI , IDE HIROSHI , TSUKANO MASAKO , WATABE YOSHIHISA
IPC分类号： H03M13/51 , G11B20/14 , H03M5/14 , H03M13/02
摘要： PROBLEM TO BE SOLVED: To obtain a record code whose distance between codes is long and also which has a short run length by receiving M-bit data and generating an N-bit code word in which a continuous number of one in a code word string is a 1st prescribed number or less and also a continuous number of zero is a 2nd prescribed number or less. SOLUTION: A magnetically recording and reproducing device 100 records data outputted from a host device 110 such as a computer on a recording medium 150, also reads data recorded on the medium 150 and outputs it to the device 110. And in a digital signal decoding device 180, an encoder 120 and a decoder 185 uses the next code. A code recorded on the device 100 usually consists of 8-bit data that is called 1 byte. For instance, when 2 bytes (16-bits) data is converted into on 17-bit record data, a code word in which continuous zeros are 10-bits at largest in any part of the code and also continuous ones are 3-bits is configured.

9. 发明专利

JP2001326564A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JP2001326564A
公开(公告)日：2001-11-22
申请号：JP2000144569
申请日：2000-05-12
申请人： HITACHI LTD
发明人： UEHARA YOICHI , YAMAMOTO KATSUMI
IPC分类号： H03K5/151 , H03K5/156 , H03L7/081 , H03L7/099
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit which restores duty to about 50% whether the duty is deviated into a state where an 'H' period is long or a state where an 'L' period is long. SOLUTION: A duty correction circuit corrects the deviation of the duty generated in converting an analog complementary periodic signal whose phase difference is about half period and whose duty ratio is about 50% to a logic level by using the NAND gate static latch of serial two stages, for example. The NAND gate static latch performs correction of about duty 50% by latching operation when the 'H' period of a complementary clock signal is long, and performs inversion operation when the 'L' period of the complementary clock signal is long. Thus, the duty is restored to about 50% with respect to both of the state where the 'H' period is long and the state where the 'L' period is long, only by logic operation from the level and timing of an inputted complementary clock signal without outputting a thin pulse equivalent to a differential waveform made by internal small delay.

10. 发明专利

JP2000113406A DECISION FEEDBACK EQUALIZER, SIGNAL PROCESSING LSI AND MAGNETIC DISK DEVICE 失效
公开(公告)号：JP2000113406A
公开(公告)日：2000-04-21
申请号：JP27707698
申请日：1998-09-30
申请人： HITACHI LTD
发明人： KATO TAKATOSHI , NISHITANI TAKUJI , KIMURA HIROSHI , UMEMOTO MASUO , UEHARA YOICHI , NARA TAKASHI , NAKAI NOBUAKI
IPC分类号： G11B5/09 , G11B20/10 , H03H17/00 , H03H21/00 , H04B3/06
摘要： PROBLEM TO BE SOLVED: To provide a decision feedback equalizer capable of reduction of decoding errors and high-speed operation of a feedback loop. SOLUTION: An anterior equalizer 100 adaptively equalizes an input signal while a discriminator 300 obtains a decoded result for the signal equalized by the anterior equalizer 100. An output signal corrector 600 obtains a corrected output signal from the input signal of the discriminator 300; an interference corrector 500 forms an interference correction signal by the decoded signal from the discriminator 300 and the corrected output signal obtained from the output signal corrector 600; and the interference correction signal is fed back to the anterior stage of the discriminator 300.

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