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    • 1. 发明专利
    • COMPUTER NETWORK SYSTEM
    • JPH09204388A
    • 1997-08-05
    • JP1154396
    • 1996-01-26
    • HITACHI LTD
    • HASHIMOTO KAZUHIRO
    • G06F1/20G06F11/30G06F13/00G06F15/16
    • PROBLEM TO BE SOLVED: To improve the reliability of a data communication controller by storing operation environment detecting information outputted from an operation environment detecting computerization means in a data message so as to transmit to a receiving side computer at the time of data communication between plural computers. SOLUTION: A data communication control part 15a within a communication side computer 11a forms a communication packet storing communication control information such as address information in a communication control information field and communication data in a communication data field according to a frame format to transmit to a data communication control part 19 as the operation detecting computerization means within a routing device 17 through a data communication line 28. The data communication control part 19 reads the communication packet, analyzes temperature information signal 26 being communication control information and operation environmental information within the communication control information field and forms the communication packet again to transmit to the receiving side computer 11b through a data communication line 27. Consequently the reliability of the whole system is improved.
    • 6. 发明专利
    • CLOCK GENERATION CIRCUIT AND BUS SYSTEM
    • JPH0798617A
    • 1995-04-11
    • JP26119993
    • 1993-10-19
    • HITACHI LTD
    • UMEMURA MASAYAOGURA TOSHIHIKONAKAJIMA KENJIHASHIMOTO KAZUHIROOKABE TOSHIHIRO
    • G06F13/42G06F1/10G11C11/407
    • PURPOSE:To reduce the clock skew of a two phase clock. CONSTITUTION:One output of a phase adjustment mechanism reaches a normal phase load point through an equal delay circuit 7 and a normal phase distribution circuit 9. A phase at the normal phase load point is inputted to a phase comparator 3 and it is compared with a reference phase. Then, a comparison signal is outputted. A variable delay circuit 5 is controlled so that the phase at the normal phase load point is matched with the phase of the reference phase in the phase comparator 3 in accordance with the comparison signal. The other output of the phase adjustment mechanism 1 becomes the clock of a delay phase by the delay means 8 of a delay phase generation system, and it reaches a delay phase load point through a delay phase distribution circuit 10. The equal delay circuit 7 delays the signal of the normal phase so that circuit delays except for delay by the delay means 8 are adjusted between the normal phase and the delay phase in a path from the output of the phase comparator 3 to the normal phase load point and the delay phase load point. The phase at the normal load point almost matches with the phase of original oscillation. The equal delay circuit 7 reduces the clock skew of the delay phase against the normal phase.
    • 7. 发明专利
    • ERROR CORRECTION CIRCUIT DIAGNOSTIC SYSTEM
    • JPH05108385A
    • 1993-04-30
    • JP26594391
    • 1991-10-15
    • HITACHI LTD
    • HASHIMOTO KAZUHIRO
    • G06F11/08G06F12/16
    • PURPOSE:To improve the reliability of the entire error correction system by instantaneously dealing with a fault of the error correction circuit by executing the error correction and normality diagnosis of detection circuits at the time of reproducing information in an information storing reproducing device parallely with the normal operation. CONSTITUTION:The error correction system consisting of an error correction code generation circuit 12, a memory 13, an error generation discrimination circuit 14, and an error correction circuit 15 and capable of correcting errors of less than N bits is provided. In the case of the generation of a correctable error in read data 24, it is corrected to output normal data 28. In the case of the generation of uncorrectable error, an error detection signal 27 is issued. An error correction circuit check circuit 17 is added to this system. The number M of bits different in uncorrected error read data 24 and corrected error read data 28 from each other is obtd. often receiving both the read data, and the number M is compared with the set value to discriminate whether or not M N, an abnormality alarm signal is outputted.
    • 9. 发明专利
    • CLOCK PHASE ADJUSTMENT SYSTEM
    • JPH08221149A
    • 1996-08-30
    • JP3043295
    • 1995-02-20
    • HITACHI LTD
    • HASHIMOTO KAZUHIRO
    • G06F1/04G06F1/08G06F1/10
    • PURPOSE: To improve the reliability of the whole system by immediately specifying whether or not an abnormal range includes the clock phase adjusting device if a fault occurs and automatically taking measures. CONSTITUTION: A counter and a selector are added to clock signal supply sources 10 and 20, and a gate logic and retry request signal generating circuit 26 which decodes the phase relation among many polyphase clocks at 25 is added to a distribution destination; and those circuits decide the normalcy of a clock for operation and if the failure in phase adjusting operation is decided, a phase adjustment retry request signal 41 is fed back to the clock signal supply source 10 to make a phase adjustment operation retry request 41. The clock signal supply source 10 counts the retry request and selects the clock for operation without performing the phase adjusting operation when a prescribed value is reached, and at the distribution destination, the system down owing to the abnormality of the clock phase is avoided by by-passing a variable delay circuit 21.