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1. 发明专利

JPH0982768A EVALUATING METHOD FOR SEMICONDUCTOR WAFER 失效
公开(公告)号：JPH0982768A
公开(公告)日：1997-03-28
申请号：JP23974695
申请日：1995-09-19
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SATO TOMOMI , SUZUKI NORIO , SHIMIZU HIROBUMI , SUGINO YUSHI
IPC分类号： G01R27/02 , H01L21/66
摘要： PROBLEM TO BE SOLVED: To make it possible to evaluate the structure and characteristics of a semiconductor wafer by measuring the change of the resistivity caused by a thermal doner generated from interlattice oxygen in the case of annealing the wafer. SOLUTION: The change of the resistivity caused by a thermal doner generated from interlattice oxygen in the case of annealing a semiconductor wafer is measured. For example, an epitaxial wafer that a p-type epitaxial layer is vapor grown on a crystal substrate (100) made of p-type single crystal silicon manufactured by a CZ method is resistance-annealed at 450 deg.C for 60 hours to generate the thermal doner in the substrate. Since the excess thermal doner is generated by the low-temperature annealing, the substrate is inverted from the p-type to the n-type. The resistivity distribution becomes as shown, and the resistivity has a point of inflection (maximum value) at the boundary between the substrate and the epitaxial layer. Accordingly, the thickness of the epitaxial layer can be obtained by knowing the distance from the surface of the epitaxial layer to the point of inflection (maximum value).

2. 发明专利

JPH07221112A MANUFACTURE OF SEMICONDUCTOR WAFER 失效
公开(公告)号：JPH07221112A
公开(公告)日：1995-08-18
申请号：JP1082194
申请日：1994-02-02
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SATO TOMOMI , SUZUKI NORIO
IPC分类号： H01L29/78 , H01L21/322
摘要： PURPOSE:To obtain an Si wafer which is very reliable near the surface of the wafer since it has a non-defect layer near the surface of the wafer and to increase the characteristics of the device such as a gate withstand strength by depositing an a-Si (amorphous silicon) layer in a specified thickness at a specified temperature on the rear face of the Si wafer. CONSTITUTION:First, an Si wafer 1 is prepared. Nextly, due to thermal decomposition of silane (SiH4), an a-Si layer 2 is formed in the thickness of about 1mum at 570-580 deg.C on the rear face of the Si wafer 1 which is a second primary face. When the wafer 1 is heat-treated, crystal defects and an oxygen deposit 6, which exist in the wafer 1, absorb impurities (a gettering action) or extinguish crystal defects due to a grain boundary generated near an interface between the wafer 1 and the a-Si layer 2, a stress of the interface such as crystallization, and a distortion field of dislocation which accompanies the stress of the interface, since the a-Si layer 2 exists on the rear face of the wafer 1.

3. 发明专利

JPH05299611A 失效
公开(公告)号：JPH05299611A
公开(公告)日：1993-11-12
申请号：JP10707292
申请日：1992-04-24
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MORI CHIEMI , IKEDA SHUJI , MEGURO SATOSHI , HASHIBA SOICHIRO , ARIGA SEIICHI , YOSHIDA YASUKO , KURAMOTO ISAMU , KANDA TAKAYUKI , MATSUKI HIROSHI , TAKAHASHI MASATO , YOSHIZUMI KEIICHI , IZAWA RYUICHI , HOSHINO YUTAKA , FUJITA ERI , SAEKI AKIRA , NAGAI KIYOSHI , SUZUKI NORIO , SATO KAZUE
IPC分类号： H01L21/768 , H01L21/8238 , H01L21/8244 , H01L27/092 , H01L27/11 , H01L29/78 , H01L29/786 , H01L21/90 , H01L29/784
摘要： PURPOSE:To take in crystal defect crossing a junction of region from an aperture end and moreover save the number of man-hours in manufacture in a semiconductor integrated circuit device where electrodes are connected through an aperture formed on an insulating film covering the surface in the source region or drain region of MISFETQd. CONSTITUTION:In a semiconductor integrated circuit device, impurity is implanted using a mask 22M to form an aperture 22 on an insulating film 21 and a semiconductor region 21N having the same conductivity type as a region 18 and having a junction depth which is deeper than that of the region 18 is formed.

4. 发明专利

JPH05299609A 失效
公开(公告)号：JPH05299609A
公开(公告)日：1993-11-12
申请号：JP10707092
申请日：1992-04-24
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MORI CHIEMI , FUJITA ERI , HOSHINO YUTAKA , SATO KAZUE , TAKAHASHI MASATO , IZAWA RYUICHI , YOSHIZUMI KEIICHI , SUZUKI NORIO , KANDA TAKAYUKI , KURAMOTO ISAMU , YOSHIDA YASUKO , HASHIBA SOICHIRO , MATSUKI HIROSHI , ARIGA SEIICHI , IKEDA SHUJI
IPC分类号： H01L27/11 , H01L21/8244 , H01L29/78 , H01L29/786 , H01L29/784
摘要： PURPOSE:To prevent damage and breakdown of a gate insulating film of MISFET and moreover improve an ON/OFF current ratio of MISFETQp in a semiconductor integrated circuit device (SRAM) comprising MISEFT having employed SOI structure. CONSTITUTION:A gate insulating film 24 of MISFETQp is mainly formed with a silicon nitride film 24C deposited by the plasma CVD method in a semiconductor integrated circuit (SRAM) comprising MTSFETQp having employed SOI structure.

5. 发明专利

JPH04335563A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH04335563A
公开(公告)日：1992-11-24
申请号：JP10705091
申请日：1991-05-13
申请人： HITACHI LTD , HITACHI VLSI ENG , HITACHI HARAMACHI SEMI CONDUCT
发明人： YOSHIZUMI KEIICHI , SATO KAZUE , TAKAHASHI MASATO , HASHIBA SOICHIRO , SUZUKI NORIO , HOSHINO YUTAKA , KANDA TAKAYUKI , YOSHIDA YASUKO , ARIGA SEIICHI , FUJITA ERI , IZAWA RYUICHI , MATSUKI HIROSHI , MORI CHIEMI , IKEDA SHUJI
IPC分类号： H01L21/8249 , H01L21/331 , H01L27/06 , H01L29/73 , H01L29/732
摘要： PURPOSE:To improve reliability and manufacturing yield of a bipolar CMOS LSI. CONSTITUTION:When a semiconductor substrate 1 is heat treated so as to form a collector leading region 13 and impurities are extended and diffused, the substrate 1 of regions for forming a base, an emitter of a bipolar transistor and a region for forming a MOSFET is covered with a silicon nitride film 7 used for formation of a field insulating film 8, thereby preventing an automatic doping with the impurities in the regions.

6. 发明专利

JPS6329575A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPS6329575A
公开(公告)日：1988-02-08
申请号：JP17165286
申请日：1986-07-23
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUZUKI NORIO , MEGURO SATOSHI , IKEDA SHUJI , MATSUDA NOZOMI
IPC分类号： G11C11/412 , H01L21/8244 , H01L27/11 , H01L29/78
摘要： PURPOSE:To improve the degree of integration of the title device and to contrive both prevention in generation of a soft error and reduction in the area of a cell by a method wherein the source and the drain regions of an MISFET are formed on the first semiconductor region which is self-matchingly formed using a mask having the size in channel length direction smaller than a gate electrode, the second high impurity region of the conductivity type opposite to that of the first region is formed along the first region and the third high impurity region of the conductivity type opposite to that of the first region is formed under the second region and the channel region. CONSTITUTION: The low impurity density semiconductor region 8A and the high density region 8B on the main surface part of an MISFET Qd, to be used for driving, constitute the source and drain regions of double drain structure. These regions 8A and 8B are constituted in a self-matching manner to an impurity introducing mask 22 using the mask 22 having the size in channel length direction smaller than a gate electrode 9. Also, the channel length of the MISFET Qs to be used for transfer is formed in the minimum working size. On the other hand, the size in channel length direction of the gate electrode 9 of the MISFET Wd for driving is formed as large as possible provided that the electrode 9 does not come in contact with the other electrode 9. Through these procedures, the area of memory cell M can be reduced, and the degree of integration of the SRAM can also be improved.

7. 发明专利

JPH09246130A SEMICONDUCTOR WAFER, MANUFACTURE THEREOF, AND MANUFACTURE OF SEMICONDUCTOR DEVICE USING IT 失效
公开(公告)号：JPH09246130A
公开(公告)日：1997-09-19
申请号：JP7839796
申请日：1996-03-06
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KANAI AKIRA , SHIMIZU HIROBUMI , SATO TOMOMI , SUZUKI NORIO
IPC分类号： H01L21/68 , H01L21/02 , H01L21/322 , H01S3/00 , H01S5/00 , H01S3/18
摘要： PROBLEM TO BE SOLVED: To provide a round wafer such that the position and crystallographic axis direction may be identified. SOLUTION: A manufacturing method of a round wafer 1 includes a longitudinal groove forming process for providing a longitudinal groove 12 in a predetermined crystal surface orientation of a block 11 ground in a columnar shape from a semiconductor ingot, a slicing process for cutting a thin plate 13 having a V-groove 14 from the block provided with the longitudinal groove, a singular property part forming process for forming a melting mark 18 having different property from other parts by irradiating the inner side of the V-groove of the thin plate with a laser 16, and a characteristic part forming process for removing the V-groove, then planarizing the main surface of the melting mark 18 and thus locally forming a characteristic part 5 having a flat surface and a different inner lattice strain 19 from the other parts, on a round semiconductor substrate 2. Thus, the round wafer may be aligned by detecting the characteristic part. With this round wafer, disorder in gas flow and thermal stress dislocation may be prevented at the time of IC manufacturing. Since the characteristic part has the inner property differing only locally, no deterioration in yield is generated.

8. 发明专利

JPH0715012A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH0715012A
公开(公告)日：1995-01-17
申请号：JP14455693
申请日：1993-06-16
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： YOSHIDA YASUKO , HASHIBA SOICHIRO , MORI CHIEMI , MATSUKI HIROSHI , FUJITA ERI , HOSHINO YUTAKA , SATO KAZUE , TAKAHASHI MASATO , YOSHIZUMI KEIICHI , IZAWA RYUICHI , SUZUKI NORIO , KANDA TAKAYUKI , KURAMOTO ISAMU , ARIGA SEIICHI , IKEDA SHUJI
IPC分类号： H01L21/265 , H01L27/088 , H01L27/11 , H01L29/784
摘要： PURPOSE:To improve characteristic of an MISFET formed on a high step- difference part or the like on a semiconductor substrate. CONSTITUTION:When a channel 19c, a source 19s and a drain 19d of an MISFET (Qp) for a load are formed by implanting impurity ions in a polycrystalline silicon film 19 deposited on the upper part of an MISFET (Qd) for driving which constitutes a memory cell of an GRAM, ion implantation is performed from the direction inclined about 45deg to the main surface of a semiconductor substrate 1, thereby making impurity concentration in the polycrystalline silicon film 19 uniform.

9. 发明专利

JPH0513700A SEMICONDUCTOR INTEGRATED CIRCUIT AND ITS FORMATION 失效
公开(公告)号：JPH0513700A
公开(公告)日：1993-01-22
申请号：JP16291491
申请日：1991-07-03
申请人： HITACHI LTD , HITACHI VLSI ENG , HITACHI HARAMACHI SEMI CONDUCT
发明人： FUJITA ERI , HOSHINO YUTAKA , SATO KAZUE , TAKAHASHI MASATO , IZAWA RYUICHI , YOSHIZUMI KEIICHI , SUZUKI NORIO , KANDA TAKAYUKI , KURAMOTO ISAMU , YOSHIDA YASUKO , HASHIBA SOICHIRO , MORI CHIEMI , MATSUKI HIROSHI , ARIGA SEIICHI , IKEDA SHUJI
IPC分类号： H01L27/10
摘要： PURPOSE:To improve electric reliability of a MISFET by making difference in height in the first region and the second region of a semiconductor layer to be used as a channel formation region of a MISFET smaller than height of lower layer protrusions. CONSTITUTION:Lower layer protrusions 7,13,15 on the first region of an underlying insulator 4 are placed. A semiconductor layer is placed which is adjacent to the lower layer protrusions 7,13,15 and the first region of the underlying insulator 4 and to be used as a channel formation region 26N of a MISFET Q over the different second region. In this semiconductor integrated circuit device, difference in height on the first region to be used as the channel formation region 26N of the MISFET Q and on the second region is made smaller than height of the lower layer protrusions 7,13,15. Thus a fluctuation in length according to the height of the lower layer protrusions 7,13,15 is reduced, thereby improving electric characteristics of the MISFET Q.

10. 发明专利

JPH04328833A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH04328833A
公开(公告)日：1992-11-17
申请号：JP9883391
申请日：1991-04-30
申请人： HITACHI LTD , HITACHI VLSI ENG , HITACHI HARAMACHI SEMI CONDUCT
发明人： TAKAHASHI MASATO , YOSHIZUMI KEIICHI , HASHIBA SOICHIRO , SUZUKI NORIO , IKEDA SHUJI , HOSHINO YUTAKA , KANDA TAKAYUKI , YOSHIDA YASUKO , ARIGA SEIICHI , FUJITA ERI , IZAWA RYUICHI , MATSUKI HIROSHI , MORI CHIEMI
IPC分类号： H01L29/73 , H01L21/331 , H01L29/732
摘要： PURPOSE:To lower the base resistance by lessening the gap between an emitter region and outer base regions of a bipolar transistor. CONSTITUTION:After the formation of an emitter electrode 9a using a cap insulating film 11a formed above an emitter region 10 as a mask, outer base regions 6a are formed in a self-alignment manner with this emitter electrode 9a thereby lessening the gap between the outer base regions 6a and the emitter region 10.

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