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1. 发明专利

JPH0982806A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH0982806A
公开(公告)日：1997-03-28
申请号：JP23793995
申请日：1995-09-18
申请人： HITACHI LTD
发明人： HONMA KENJI , OMORI SOHEI , TANBA NOBUO
IPC分类号： G01R31/302 , H01L21/3205 , H01L21/66 , H01L21/82 , H01L21/822 , H01L23/52 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To give a decision whether a power source wiring system is defective or non-defective during a wiring formation process, and to correct the defective part of the power source wiring from the result of said decision by a method wherein the power source wiring is inspected by an electron beam tester during the wiring forming process of a semiconductor integrated circuit device. SOLUTION: A power source wiring block 7, consisting of a plurality of power source wirings 8a, 8a1 , 8a2 , 8b, 8b1 and 8b2 , is formed on a part of the prescribed wiring layer on a semiconductor substrate. Subsequently, power feeding blocks P1 and P2 are brought into contact with the power feeding pats 8P1 and 8P2 of the power source wiring block 7. An electron beam is swept over with a prescribed voltage applied to the power source wirings 8a and 8b from the power feeding probes P1 and P2 through the power feeding pats 8P1 and 8P2 , the secondary electron, radiated from the power source wiring block 7, is detected by a secondary electron detector, and the short circuit of the power source is checked. When a defect is discovered, the reclaimability of the short-circuited part is examined and when it is reclaimable, a reclamation treatment is conducted after the inspection on the power source wiring block 7 has been finished.

2. 发明专利

JPH0897710A PROGRAMMABLE TWO-WIRE TWO-PHASE SYSTEM LOGIC ARRAY 失效
公开(公告)号：JPH0897710A
公开(公告)日：1996-04-12
申请号：JP25880994
申请日：1994-09-28
申请人： HITACHI LTD
发明人： MASAKI AKIRA , KUWATA MAKOTO , SATOMURA RYUICHI , TANBA NOBUO
IPC分类号： G06F7/00 , H01L21/82 , H03K19/173 , H03K19/177
摘要： PURPOSE: To realize the logic array by which a 2-wire 2-phase system practical circuit configuration is promoted by providing a memory cell whose writing is made electrically or as a process and providing a function output corresponding to one or plural input signals to the array. CONSTITUTION: A contact (memory cell) is provided selectively to each cross point between each function row output and each of 2-wire 2-phase system input signal wire pairs I1+ , 11- -In+ , In- among input and output wires corresponding to an AND function. For example, a contact is provided to three input signal wires I1+ , I2+ and In- of a 1st function output row. In order that a function output from the three input signal wires 11+ , I2+ and In- is obtained, a contact is respectively provided to a cross point of a code word state detection row corresponding to the three input signal wires with respect to wires for state detection signals C1, C2 and Cn corresponding to the three input wires. According to the means, the 2-wire 2-phase system logic array is directly realized by the same method as a PLA (programmable logic array) without conversion into a 2-wire 2-phase system logic circuit after circuit design different from a conventional array.

3. 发明专利

JPH0774098A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH0774098A
公开(公告)日：1995-03-17
申请号：JP15972893
申请日：1993-06-29
申请人： HITACHI LTD
发明人： KASAI MOTOKI , TANBA NOBUO , HIRAMOTO TOSHIRO , ODAKA MASANORI , IKEDA TAKAHIDE
IPC分类号： H01L27/06 , H01L21/06 , H01L21/331 , H01L21/8249 , H01L27/12 , H01L29/73
摘要： PURPOSE:To retain the high-speed operation property of a MOS transistor, and improve the flattening of the whole substrate and the accuracy in processing when constituting a BiCMOS type of LSI by forming the MOS transistor and a bipolar transistor on a film SOI. CONSTITUTION:An oxide film 2 and a silicon film 3 are formed on a silicon substrate 1, and the n-type diffusion layer 22 of the silicon film constitutes the collector region of a bipolar transistor, and a collector lead electrode is constituted of an n -type diffusion layer 21 surrounding this and a polycide film 23 on it, and a p-type base region 25 to contact with the collector region is made inside the opening of the oxide film 24 on the collector region, and an n-type emitter region to contact with the base region is made inside the opening of the oxide film 26 on the base region. Hereby, the bipolar transistor is made of a film as thick as the MOS transistor, and the flattening between both is achieved.

4. 发明专利

JPH06162783A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH06162783A
公开(公告)日：1994-06-10
申请号：JP33010792
申请日：1992-11-16
申请人： HITACHI LTD
发明人： KURITA KOZABURO , TANBA NOBUO
IPC分类号： G11C11/413 , G11C11/414
摘要： PURPOSE:To increase the capacity and to reduce the power consumption by reducing the operating current especially in the non-selected state of an ECL CMOS static RAM or the like. CONSTITUTION:Address selecting MOSFETs which selectively connect memory cells MC constituting a memory array MARY of the ECL CMOS static RAM or the like and corresponding complementary bit lines B0* to Bn* consist of p-channel MOSFETs P3 and P4, for example. The non-selection level of word lines W0 to Wm is set to the level at which the discharge circuit of word line driving circuits is made to be in the turning-off state, namely, the high level. Thus, when word lines W0 to Wm are made to be in the non-selected state, the quantity of the current flowing through discharge circuits of corresponding word line driving circuits is reduced.

5. 发明专利

JPH0653422A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND FABRICATION THEREOF 失效
公开(公告)号：JPH0653422A
公开(公告)日：1994-02-25
申请号：JP20100192
申请日：1992-07-28
申请人： HITACHI LTD
发明人： KIKUCHI TOSHIYUKI , NISHIZAWA HIROTAKA , IKEDA TAKAHIDE , HIRAMOTO TOSHIRO , TANBA NOBUO
IPC分类号： H01L27/06 , H01L21/8238 , H01L21/8249 , H01L27/092
摘要： PURPOSE:To fabricate a semiconductor integrated circuit device having CMOS or BiCMOS structure with high integration. CONSTITUTION:In a semiconductor integrated circuit device having CMOS or BiCMOS structure, implantation of impurities for forming CMOS region, i.e., N-well and P-well, is performed through self-aligned manner for an isolation region, i.e., a field isolation film 23 and an isolation groove 24, after formation thereof.

6. 发明专利

JPH05307897A 失效
公开(公告)号：JPH05307897A
公开(公告)日：1993-11-19
申请号：JP13982192
申请日：1992-05-01
申请人： HITACHI LTD
发明人： TANBA NOBUO , OBAYASHI MASAYUKI , HIRAMOTO TOSHIRO
IPC分类号： G11C29/00 , G11C29/04 , H01L27/10
摘要： PURPOSE:To maintain the high speed of operation regardless of the presence of defect saving by using a MOBFET and switching the transfer path of an address signal with a redundant signal and outputting a defect signal with an auxiliary circuit. CONSTITUTION:The redundant signal is supplied to the gate of a P channel type MOSFET QP through an N channel type MOSFET QN and an inverter circuit IV. Then, when the redundant signal is a high level, both transistors QN and QP are turned on and when a low level, turned off. In such a case, in the state of cutting a fuse, the redundant signal becomes the low level and the transistor QP1 is turned off and an inout signal ELC1 is not transferred to an output terminal OUT1. At this time, the transistor QP2 is turned on and the input signal ELC2 is outputted to the output terminal OUT2. Then the defect circuit having the redundant signal is switched to the corresponding auxiliary circuit and the high speed of operation is maintained since the number of logic stage is made equal regardless of the presence of the defect saving.

7. 发明专利

JPH04276385A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH04276385A
公开(公告)日：1992-10-01
申请号：JP6264691
申请日：1991-03-04
申请人： HITACHI LTD
发明人： TANBA NOBUO , OBAYASHI MASAYUKI , HIRAMOTO TOSHIRO , SAITO KAYOKO , ODAKA MASANORI
IPC分类号： G11C11/417 , G11C11/413 , G11C11/414 , G11C11/415
摘要： PURPOSE:To make fast the action speed by securing the level necessary to an output amplitude by a current switch circuit and driving directly an output transistor through an emitter follower circuit. CONSTITUTION:By a current switch circuit including differential transistors Q1-Q3 to receive input signals XD1 and XD2 and a reference voltage VBB, amplifying is performed to the necessary signal level, and a pair of complementary output signals ob and ot are inputted to a pair of emitter follower transistors Q5 and Q4. By the output signal of a transistor Q5, an emitter follower output transistor Q6 is driven, an N channel type MOSEFETMN is driven by the output signal of a transistor Q4, and from the emitter of a transistor Q6, the level-amplified output signal is formed. By such a configuration an action can be made fast by the simple circuit that the output transistor Q6 is driven through the emitter follower circuit directly.

8. 发明专利

JPH04182988A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH04182988A
公开(公告)日：1992-06-30
申请号：JP31092590
申请日：1990-11-16
申请人： HITACHI LTD , HITACHI HARAMACHI SEMI CONDUCT
发明人： OBAYASHI MASAYUKI , SHIODA MASASHI , TANBA NOBUO
IPC分类号： G11C11/413 , G11C29/00 , G11C29/04
摘要： PURPOSE:To allow the effective relief of defective bits without increasing access time with reduced electric power consumption by dividing memory cell arrays to plural blocks and adding a spare memory block of the same capacity as the capacity of these blocks. CONSTITUTION:Reading out/writing circuits 5a to 5h corresponding to the normal memory blocks and a reading out/writing circuit 5R corresponding to the spare memory block 1R are made of the same constitution. In addition, a Y system decoder-driver 3 is formed to such a shape which handles the changeover signal from a defect block changeover signal generating circuit 4 as the signal equal to an address signal and generates the selection signal for the memory blocks. Then, the critical path to determine the access time of the normal memory blocks 1a to 1h and the spare memory block 1R are exactly the same. The increase in the access time by the adoption of the redundancy constitution is obviated in this way.

9. 发明专利

JPH03205869A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH03205869A
公开(公告)日：1991-09-09
申请号：JP69090
申请日：1990-01-08
申请人： HITACHI LTD
发明人： TANBA NOBUO
IPC分类号： H01L27/11 , H01L21/8244
摘要： PURPOSE:To obtain a technology capable of reducing soft errors in a semiconductor integrated circuit device having SRAM by providing the top of a protruding island region spreading over the element-forming face of a semiconductor substrate with transfer MISFETs, and the side wall of the above-mentioned island region with drive MISFETs of a flip-flop circuit. CONSTITUTION:In a semiconductor integrated circuit device having SRAM constituting a memory cell by connecting transfer MISFETs QT1, QT2 to the input terminals of a flip-flop made up of drive MISFETs QD1 QD2, the top of a protruding island region 4 spreading over the element-forming face of a semiconductor substrate 11 is provided with transfer MISFETs QT1, QT2, and the side wall of the above-mentioned protruding island region 4 with drive MISFETs QD1, QD2 with source regions 2 arranged below a semiconductor region 11 that serves as the information storage node of the transfer MISFETs QT1, QT2. This design reduces the depth of a p-type well region 5 with the result that the region where electron-hole pairs occur upon passage of alpha rays decreases; therefore, soft errors caused by alpha rays can be reduced.

10. 发明专利

JPS6457650A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6457650A
公开(公告)日：1989-03-03
申请号：JP21457087
申请日：1987-08-27
申请人： HITACHI LTD
发明人： UDA TAKAYUKI , EMOTO YOSHIAKI , TANAKA TAMOTSU , KURODA SHIGEO , MIYAOKA SHUICHI , TANBA NOBUO
IPC分类号： H01L23/29 , H01L23/31
摘要： PURPOSE:To prevent the soft error in a semiconductor device of salient electrode mounting system, and lengthen the connecting life of the salient electrode, by arranging a coating film for shielding alpha-ray on a semiconductor chip or a specified part of a mounting substrate surface excepting salient electrode parts. CONSTITUTION:A coating film 3 for shielding alpha-ray is arranged on a semiconductor chip 1 or a specified part of a mounting substrate surface excepting salient electrode parts 4 for face down bonding. For example, only the surface of a memory mat region 2, which is especially weak for soft error in the semiconductor chip 1 of a semiconductor device having an element in which both bipolar transistors and COMS's exist, is coated with a coating film 3 for shielding alpha-ray which is composed of polyimide resin. The part of the salient electrodes 4 composed of solder bump and the like are not coated. The semiconductor chip 1 is mounted on the mounting substrate 5 via the salient electrodes 4. As a result, difference of thermal expansion coefficient between the protruding electrodes and the resin does not exert influence upon the salient electrodes. Thereby lengthening connection of life of the salient electrode.

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