专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JPS634314A POWER SOURCE TURNING-ON SYSTEM 失效
公开(公告)号：JPS634314A
公开(公告)日：1988-01-09
申请号：JP14687086
申请日：1986-06-25
申请人： HITACHI LTD
发明人： HAYASHI TAKAHIDE
IPC分类号： G06F1/26 , G06F1/00
摘要： PURPOSE:To turn on the power source of a center computer from a terminal by providing a means which confirms that the center computer transmits and receives data to and from none of terminals to a system where plural terminals are connected on the same interface. CONSTITUTION:When the power source of a terminal 8 is turned on, a terminal processor part 13 instructs the start of time monitoring and also waits for a polling sequence, acknowledgement data or negative acknowledgement data to be sent from the center computer 1. A timer 10 monitors the time and holds the output of a transmission gate 18 at '0' for 10sec through a level variation part 11 when detecting 60sec having passed. The level variation detection part 7 on the side of the center computer 1, on the other hand, turns on a power source 3 through a signal line 17 when detecting the level being held for 5sec, thereby allowing the center computer 1 to start operating.

2. 发明专利

JPS5668847A DATA PROCESSOR 失效
公开(公告)号：JPS5668847A
公开(公告)日：1981-06-09
申请号：JP14503779
申请日：1979-11-09
申请人： HITACHI LTD
发明人： YAMAMOTO JIYUNICHI , YAMAGISHI MASATO , IWAMOTO SHIYOUJI , TAKAHASHI SAKAE , HAYASHI TAKAHIDE
IPC分类号： G06F9/34 , G06F9/30 , G06F9/32 , G06F12/02 , G06F13/00
摘要： PURPOSE:To obtain an address space double as large as that limited by the basic word length, by using the carry bit caused in the addition of a base register for the highest rank bit. CONSTITUTION:When the EMA signal shown in the diagram becomes ''1'' in the case of the address extention mode, the carry signal of the arithmetic circuit 19 is supplied to the data input terminal of the FF23 via tha AND gate 25. Then the output 1 bit of the FF23 is connected to the highest rank bit of the memory address output gate 24 of 17 bits, and all bits (16 bits) of the memory address register 22 are connected to the lower rank 16 bits each. Thus an address space double as large as that limited by the basic word length can be obtained by using the carry bit FF23 for the highest rank bit of the address.

3. 发明专利

JPS5650441A DATA PROCESSING SYSTEM 失效
公开(公告)号：JPS5650441A
公开(公告)日：1981-05-07
申请号：JP12540679
申请日：1979-10-01
申请人： HITACHI LTD
发明人： HAYASHI TAKAHIDE , YAMAMOTO JIYUNICHI , YAMAGISHI MASATO , HASEGAWA SAKAE , DOUMEN NOBUYOSHI
IPC分类号： G06F9/34 , G06F9/30 , G06F12/02 , G06F13/00
摘要： PURPOSE:To read out instruction words in the extended space by a program counter of no capacity, by causing the processor itself to store instruction words of an instruction group other than the normal instruction group in the extended address and to address instruction words by the address smaller than the extended address. CONSTITUTION:Locations 0-64kW of the memory are used as basic address space 28, and locations 64-128kW are used as extended address space 29, and control program 30, decoding program 31, and a part of the beginning of object program 32 are stored in space 28. Program 32 is stored in space 29, and this program 32 is described with OI instructions 33 other than instructions of the data processor. These instructions 33 are decoded by decoding program 31 to make it possible that the processor itself executes them, and instruction words are addressed by the address smaller than the extended address and can be read out by the program counter.

4. 发明专利

JPS5420631A SIGNAL CONNECTION SYSTEM OF LOGIC CIRCUIT 失效
公开(公告)号：JPS5420631A
公开(公告)日：1979-02-16
申请号：JP8504377
申请日：1977-07-18
申请人： HITACHI LTD
发明人： TSUCHIDA HACHIO , HAYASHI TAKAHIDE , HOSHINA KIYOSHI
IPC分类号： H03K19/0175 , H03K19/00
摘要： PURPOSE:To improve the mounting efficiency of a logic substrate, by connecting a series of identical-number pins equivalent to a common signal to a plural number of blocks of connectors into which respective logic substrates are inserted.

5. 发明专利

JPS5179521A 失效
公开(公告)号：JPS5179521A
公开(公告)日：1976-07-10
申请号：JP437175
申请日：1975-01-08
申请人： HITACHI LTD
发明人： SHIMURA SHIGEO , HAYASHI TAKAHIDE , MOGI FUMIO , DAIZO NOBORU
IPC分类号： H04L1/00 , G06F3/00 , G06F11/00 , G06F11/22 , G06F13/00 , H04L29/14

6. 发明专利

JPS6419489A HANDWRITTEN CHARACTER INPUT DEVICE 失效
公开(公告)号：JPS6419489A
公开(公告)日：1989-01-23
申请号：JP17462887
申请日：1987-07-15
申请人： HITACHI LTD , HITACHI CHUBU SOFTWARE KK
发明人： KONISHI YOSHIHARU , SUZUKI NORIO , MATSUDA TOSHIHIKO , HAYASHI TAKAHIDE
IPC分类号： G06K9/62 , G06K9/03 , G06K9/68
摘要： PURPOSE:To easily input both character styles of an old KANJI (Chinese character) and a KANJI in common use, by inputting a known character, and converting it to the other character style, even when an operator knows only one of the old KANJI and the KANJI in common use. CONSTITUTION:A character code converting part 15 consists of a character recognizing part 6 for analyzing a coordinate data from a tablet 1 and recognizing a character, etc., a memory 7 for storing a dictionary for recognizing its character, an old KANJI/KANJI-in-common use converting part 8, a memory 9 for storing its conversion table, and a character style selecting part 10 for displaying the old KANJI on a CRT 16 and selecting a character style outputted to the outside. In this state, with respect to a KANJI character code which is recognized by a handwriting input to a device, the corresponding old KANJI, and the corresponding KANJI in common use are displayed in case of the KANJI in common use in which the old KANJI exists, and in case of the old KANJI, respectively, and it is selected by an operator. In such a way, even when the operator knows only one character style of the KANJI in common use and the old KANJI, the other character style can be easily inputted and the input efficiency is improved.

7. 发明专利

JPS619643B2 JPS619643B2 - 失效
公开(公告)号：JPS619643B2
公开(公告)日：1986-03-25
申请号：JP14503779
申请日：1979-11-09
申请人： Hitachi Ltd
发明人： YAMAMOTO JUNICHI , YAMAGISHI MASATO , IWAMOTO SHOJI , TAKAHASHI SAKAE , HAYASHI TAKAHIDE
IPC分类号： G06F9/34 , G06F9/30 , G06F9/32 , G06F12/02 , G06F13/00

8. 发明专利

JPS6373315A POWER SOURCE APPLYING SYSTEM 失效
公开(公告)号：JPS6373315A
公开(公告)日：1988-04-02
申请号：JP21713986
申请日：1986-09-17
申请人： HITACHI LTD
发明人： HAYASHI TAKAHIDE
IPC分类号： G06F1/26 , G06F1/00
摘要： PURPOSE:To surely perform the application of a power source from a terminal to a computer, by providing a means which detects the fact that no data transmission from a center computer is performed for a constant time, and a means which transmits a power source application request to the computer only when the above state is detected, at the terminal, and providing a reception detecting means and a power source applying means, at a computer side. CONSTITUTION:In the center computer 1, a power source 3 is applied by the operation of an operator ordinarily, and the power source is supplied to a processor 2 through a signal line 16, and the processor 2 is placed under a state possible to be operated, and a polling sequence with a time interval of one second set in a timer 10, is transmitted to terminals 8 and 8' through a signal line 14, a transmission part 15, and a signal line 19. Also, in a terminal processor 13, a time monitoring stop signal is supplied to the timer 10 through a terminal reception part 9, and signal lines 23 and 24, and when data to be transmitted to the computer 1 is present, transmission data is transmitted from its own terminal through a signal line 25, a terminal transmission part 12, and a signal line 20. Thus, the transmission data is transferred to the processing part 2 through a reception part 6, and a signal line 15, and after processing in the day are completed, the power source 3 is turned off automatically.

9. 发明专利

JPS5583940A ORDER EXTENSION SYSTEM 失效
公开(公告)号：JPS5583940A
公开(公告)日：1980-06-24
申请号：JP15640078
申请日：1978-12-20
申请人： HITACHI LTD
发明人： HAYASHI TAKAHIDE , KOBAYASHI SATOSHI , MAGARIDA YUTAKA , YONEMURA MASATOSHI , TSUCHIYA CHIHIRO
IPC分类号： G06F9/22
摘要： PURPOSE:To increase the types of orders substantially for the processor of the microprogram control system by giving execution to the optional order word read out of the main memory in the form of plural different orders and without giving any alteration to the constitution of the order word. CONSTITUTION:Main memory 1 is connected to order register 3 which memorizes the order word read out via signal line 2 and furthermore to address generator circuit 5 via signal line 4. The output of circuit 5 is transferred to address alteration circuit 7 via signal line 6, and the output is transferred to microprogram counter 9 via signal line 8. And the output of counter 9 is connected to microprogram memory device 11 via signal line 10. The microorder read out of device 11 is transferred to microorder register 13 via signal line 12, and the output is applied to microorder execution circuit 15 via signal line 14. Furthermore, signal line 16 which is led from circuit 15 and designates the alteration state of circuit 7 is connected to address alteration register 17.

10. 发明专利

JPS522217A RETRIAL PERFORMING SYSTEM IN OUTPUTTING MEANS 失效
公开(公告)号：JPS522217A
公开(公告)日：1977-01-08
申请号：JP7668875
申请日：1975-06-24
申请人： HITACHI LTD
发明人： SHIMURA SHIGEO , HAYASHI TAKAHIDE
IPC分类号： G06F11/14 , B41J29/38 , G06F11/00 , G06K15/00 , G06K15/10
摘要： PURPOSE:To alleviate abnormality restoring performance in outputting means in a treatment apparatus by performing output retrial only in the outputting means side, while the output data is secured in the outputting means side.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式