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1. 发明专利

JPS58213320A Data processor 失效
标题翻译：数据处理器
公开(公告)号：JPS58213320A
公开(公告)日：1983-12-12
申请号：JP9484382
申请日：1982-06-04
申请人： Hitachi Ltd
发明人： YAMAGISHI MASATO
IPC分类号： G06F1/00 , G06F9/445
CPC分类号： G06F9/445
摘要： PURPOSE:To save the capacity of a microprogram, by using a switch function in an operating panel for loading an initial program, in a data processor having an initial program load mechanism. CONSTITUTION:In depressing a switch 1, a signal 7 is outputted and switches 2-5 are inhibited. As soon as a signal 9 is outputted, a signal (60)16 is outputted to 16-bit of a signal 12 and set to an address register. When a signal 10 is outputted, a value to be written in the address (60)16 of a main storage is outputted to 16-bit of the signal 12. A required value is written in the address (60)16 of the main storage and the value of the address register is added by 1 and a prescribed program is written from the address 60(16) to a (DF)60. A signal (60)16 is outputted to the signal 12 together with the signal 11 finally, and the execution is started from a value written in the address (60)16 of the main storage with this signal.
摘要翻译：目的：通过在操作面板中使用开关功能来加载初始程序来节省微程序的容量，在具有初始程序加载机制的数据处理器中。构成：在按下开关1时，输出信号7，禁止开关2-5。一旦输出信号9，就将信号（60）16输出到信号12的16位并设置到地址寄存器。当输出信号10时，要写入主存储器的地址（60）16的值被输出到信号12的16位。所需值被写入主存储器的地址（60）16 并且将地址寄存器的值加1，并将规定的程序从地址60（16）写入（DF）60。最终将信号（60）16与信号11一起输出到信号12，并且利用该信号从写入主存储器的地址（60）16的值开始执行。

2. 发明专利

JPS5969827A Data processor 失效
标题翻译：数据处理器
公开(公告)号：JPS5969827A
公开(公告)日：1984-04-20
申请号：JP17984482
申请日：1982-10-15
申请人： Hitachi Ltd
发明人： YAMAGISHI MASATO , HORI KAZUYA , FUJIOKA YOSHINORI
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： PURPOSE:To prevent a main memory device from overline by providing the titled device with a buffer content monitoring circuit and controlling and interrupting an instruction decoding circuit in a central processing unit (CPU) by monitoring information from said monitoring circuit. CONSTITUTION:If an I/O device (I/O) 2 outputs a using request of a DMA at the transmission/reception of plural continuous data between the CPU1 and MM3, the capacity of a DMA bus is limited and a DMA bus using right controlling circuit 5 in the CPU1 outputs a suspending instruction to said using request. Since the I/O 2 can not use the DMA bus, data are accumulated in a transmissuon/reception buffer 10. When the accumulated variable exceeds a fixed value, a buffer content monitoring circuit 13 sets a signal 12 and interrupts the operation of the instruction decoding circuit 7. If the I/O 2 outputs the DMA bus using request under the interrupted state, the DMA bus using right controlling circuit 5 in the CPU1 outputs a using permission immediately, so that data can be transferred from a data transfer circuit 9 to the MM3 by using the DMA bus.
摘要翻译：目的：通过向标题设备提供缓冲内容监控电路，通过监控来自所述监控电路的信息来控制和中断中央处理单元（CPU）中的指令解码电路，防止主存储器件过线。构成：如果I / O设备（I / O）2在CPU1和MM3之间的多个连续数据的发送/接收时输出DMA的使用请求，DMA总线的容量受限制，使用正确的DMA总线 CPU1中的控制电路5向所述使用请求输出暂停指令。由于I / O 2不能使用DMA总线，所以数据被存储在传送/接收缓冲器10中。当累加变量超过固定值时，缓冲内容监视电路13设置信号12并中断指令的操作解码电路7.如果I / O 2在中断状态下使用请求输出DMA总线，则使用CPU1中的右控制电路5的DMA总线立即输出使用许可，从而可以从数据传送电路9传送数据通过使用DMA总线到MM3。

3. 发明专利

JPS5638649A DATA PROCESSING SYSTEM 失效
公开(公告)号：JPS5638649A
公开(公告)日：1981-04-13
申请号：JP11418979
申请日：1979-09-07
申请人： HITACHI LTD
发明人： YAMAGISHI MASATO , FUJIOKA YOSHINORI
IPC分类号： G06F13/12 , G06F3/00 , G06F12/10 , G06F13/00
摘要： PURPOSE:To enable the data access in high speed, by the constitution of the memory unit connected with the processor and channel unit via the buses and enabling the buffer unit in the processor with logic address to be directly accessed. CONSTITUTION:The processor 8', channel unit 4, and memory unit 12 are connected with the address line transferring the logic address, and the associative memory unit 13 and the main storage 5 are connected with the real address line. In the processor 8', the processing unit accesses the buffer storage 11 at the logic address with the support of the directory unit 9 and the comparator 10, and if the data requested to the buffer storage 11 is absent, it is delivered to the associative memory 2 via the address bus 6 and the main storage 5 is accessed through the conversion into real address here.

4. 发明专利

JPS5578349A ERROR DETECTION SYSTEM 失效
公开(公告)号：JPS5578349A
公开(公告)日：1980-06-12
申请号：JP15102778
申请日：1978-12-08
申请人： HITACHI LTD
发明人： YAMAGISHI MASATO
IPC分类号： G06F11/00
摘要： PURPOSE:To detect malfunctions of a micro address register or peripheral circuits of it by providing information for checking errors of contents of this register in micro instructions and checking errors of contents of this register. CONSTITUTION:Micro address register 4 stores addresses of a microprogram, and memory 1 stores micro instructions having information for detecting errors of register 4. Meanwhile, micro address check register 7 sets information for detecting errors, and check circuit 9 uses this set information to detect errors of contents of register 4. Thus, malfunctions of register 4 and peripheral circuits of it can be detected.

5. 发明专利

JPS5371544A ABNORMAL LOOP DETECTION CIRCUIT FOR MICROPROGRAM 失效
公开(公告)号：JPS5371544A
公开(公告)日：1978-06-26
申请号：JP14648076
申请日：1976-12-08
申请人： HITACHI LTD
发明人： YAMAGISHI MASATO , FUJIOKA YOSHINORI
IPC分类号： G06F11/30 , G06F9/22 , G06F11/00
摘要： PURPOSE:To tell the operator the fault and to reduce the fault detection time, by providing the counter counting at a given period so that the abnormity is detected in a given time if the microprogram is in abnormal loop.

6. 发明专利

JPS52132751A OPERATIONAL UNIT 失效
公开(公告)号：JPS52132751A
公开(公告)日：1977-11-07
申请号：JP4856776
申请日：1976-04-30
申请人： HITACHI LTD
发明人： YAMAGISHI MASATO , YAMAMOTO JIYUNICHI
IPC分类号： G06F7/537 , G06F7/508 , G06F7/535
摘要： PURPOSE:To enable high speed division, by shortening the shift time required for the division.

7. 发明专利

JPS522141A INTERRUPTION CONTROL SYSTEM 失效
公开(公告)号：JPS522141A
公开(公告)日：1977-01-08
申请号：JP7664675
申请日：1975-06-24
申请人： HITACHI LTD
发明人： MORIKAWA KIKUO , NAKAMURA SHINICHI , YAMAGISHI MASATO
IPC分类号： G06F9/48 , G06F9/30
摘要： PURPOSE:To provide an interruption control system which does not need to have unnecessary region of main memory.

8. 发明专利

JPS5160427A Deetashorisochi 失效
公开(公告)号：JPS5160427A
公开(公告)日：1976-05-26
申请号：JP13366974
申请日：1974-11-22
申请人： Hitachi Ltd
发明人： NAKAMURA SHINICHI , MORIKAWA KIKUO , YAMAGISHI MASATO
IPC分类号： G06F9/38 , G06F3/00 , G06F9/48

9. 发明专利

JPS6183048A Image data rotary apparatus 失效
标题翻译：图像数据旋转设备
公开(公告)号：JPS6183048A
公开(公告)日：1986-04-26
申请号：JP20531284
申请日：1984-09-29
申请人： Hitachi Ltd
发明人： KOMORI KAZUHIKO , YAMAGISHI MASATO , UCHIUMI KAZUHIKO
IPC分类号： G06F3/12 , B41J2/485 , G06K15/12 , G06T3/60
CPC分类号： G06K15/128
摘要： PURPOSE:To enable high speed processing, by simultaneously perform the output operations of image data after the length and breadth conversion of the image data stored in an image data memory part and that in an output mechanism part enabling high speed output. CONSTITUTION:The command data received in a circuit control part 3 through a circuit is transmitted to a main memory part 4 and the image data corresponding to a data development control part 5 is written in an image data memory part 9 by the order of CPU1. By the control of an image data rotation control part 20, the image data outputted to the printing mechanism part 19 is stored in an output data memory part 13 at first. Thereafter, the image data in the memory part 9 is rotated by 90 deg. to simultaneously perform the operation for transmitting image data to one of the output data memory parts 13, 14 and the printing operation of the printing mechanism 19 based on the output from the memory parts 13 or 14. Therefore, high speed processing is enabled without lowering the processing capacity of the printing mechanism 19.
摘要翻译：目的：通过在存储在图像数据存储器部分中的图像数据的长度和宽度转换之后同时执行图像数据的输出操作以及能够进行高速输出的输出机构部件中来实现高速处理。构成：通过电路在电路控制部分3中接收到的命令数据被发送到主存储器部分4，并且与数据显影控制部分5对应的图像数据按照CPU1的顺序写入图像数据存储器部分9。通过图像数据旋转控制部20的控制，首先将输出到打印机构部19的图像数据存储在输出数据存储部13中。此后，将存储器部分9中的图像数据旋转90度。基于存储部13或14的输出，同时进行将图像数据发送到输出数据存储部13,14之一的操作和打印机构19的打印动作。因此，能够进行高速处理而不降低打印机构19的处理能力。

10. 发明专利

JPS5650441A DATA PROCESSING SYSTEM 失效
公开(公告)号：JPS5650441A
公开(公告)日：1981-05-07
申请号：JP12540679
申请日：1979-10-01
申请人： HITACHI LTD
发明人： HAYASHI TAKAHIDE , YAMAMOTO JIYUNICHI , YAMAGISHI MASATO , HASEGAWA SAKAE , DOUMEN NOBUYOSHI
IPC分类号： G06F9/34 , G06F9/30 , G06F12/02 , G06F13/00
摘要： PURPOSE:To read out instruction words in the extended space by a program counter of no capacity, by causing the processor itself to store instruction words of an instruction group other than the normal instruction group in the extended address and to address instruction words by the address smaller than the extended address. CONSTITUTION:Locations 0-64kW of the memory are used as basic address space 28, and locations 64-128kW are used as extended address space 29, and control program 30, decoding program 31, and a part of the beginning of object program 32 are stored in space 28. Program 32 is stored in space 29, and this program 32 is described with OI instructions 33 other than instructions of the data processor. These instructions 33 are decoded by decoding program 31 to make it possible that the processor itself executes them, and instruction words are addressed by the address smaller than the extended address and can be read out by the program counter.

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