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1. 发明专利

JP2006259869A Multiprocessor system 审中-公开
标题翻译：多处理器系统
公开(公告)号：JP2006259869A
公开(公告)日：2006-09-28
申请号：JP2005073300
申请日：2005-03-15
申请人： Fujitsu Ltd , 富士通株式会社
发明人： YAMAGUCHI KUNIO , KAWASAKI NAOKI , NOYAMA MITSUHIRO , KAWAMOTO SHINJI
IPC分类号： G06F11/34
CPC分类号： G06F11/0784 , G06F11/0724 , G06F11/0778 , G06F11/3476
摘要： PROBLEM TO BE SOLVED: To provide a multiprocessor system capable of analyzing collaborative motion of all processors before failure when the failure occurs, with respect to the multiprocessor system where the plurality of processors 2_1-2_n are managed by a management processor 1, and accessing to a common memory 3 is controlled by a bus control device 4.
SOLUTION: The management processor 1 or the bus control device 4 provides each of the processors 2_1-1_n with time information synchronized in starting the system, and the processors 2_1-2_n respectively collect self-travel history information related to the time information. When each of the processors 2_1-2_n detects the failure, it stops the self-travel history information and notifies the other processors of the detection of failure to stop their travel history information. Each of the processors 2_1-2_n stops the collection of the self-travel history information, and stores the self-travel history information in a nonvolatile memory 13 provided besides the common memory 3.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种能够在故障发生之前分析故障之前的所有处理器的协同运动的多处理器系统，对于多处理器2_1-2_n由管理处理器1管理的多处理器系统，并且访问公共存储器3由总线控制装置4控制。解决方案：管理处理器1或总线控制装置4为每个处理器2_1-1_n提供在启动系统时同步的时间信息，并且处理器2_1-2_n分别收集与时间信息相关的自旅行历史信息。当处理器2_1-2_n中的每一个检测到故障时，它停止自行车历史信息，并通知其他处理器检测到故障以停止其旅行历史信息。每个处理器2_1-2_n停止收集自行车历史信息，并将自行车历史信息存储在除了公共存储器3之外提供的非易失性存储器13中。（C）2006，JPO＆NCIPI

2. 发明专利

JP2008046685A Duplex system and system switching method 审中-公开
标题翻译：双重系统和系统切换方法
公开(公告)号：JP2008046685A
公开(公告)日：2008-02-28
申请号：JP2006218898
申请日：2006-08-10
申请人： Fujitsu Ltd , 富士通株式会社
发明人： TSUKIJI HIDEKAZU , KAWASAKI NAOKI , YAMAGUCHI KUNIO , UEMURA KAZUNORI , TAMURA RIYOUKO
IPC分类号： G06F12/08 , G06F12/16
CPC分类号： G06F11/2043 , G06F11/2038 , G06F11/2097 , G06F12/0844 , G06F12/0853
摘要： PROBLEM TO BE SOLVED: To provide a duplex system and a system switching method for matching the content of cache memories loaded on both processors when update processing to the cache memories is operated by performing reading and writing through a plurality of ports for the cache memories. SOLUTION: This duplex system is configured to monitor the occurrence of a failure in any of an operational processor 20a and a standby processor 20b, and to, when a failure occurs in the operational processor, switch to the standby processor. A cache memory of each processor has a plurality of ports through which data can be simultaneously read and written. The cache memory controller of the operational processor transfers the update data for the cache memory to the cache memory of the standby processor by using a port different from the port used for updating. The cache memory controller of the standby processor writes the received update data into the cache memory by using a port different from the port used for updating. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种双工系统和系统切换方法，用于通过对多个端口进行读取和写入，来操作对高速缓冲存储器的更新处理时，将加载在两个处理器上的高速缓存存储器的内容进行匹配，缓存记忆解决方案：该双工系统被配置为监视任何操作处理器20a和备用处理器20b中的故障的发生，并且当在操作处理器中发生故障时切换到备用处理器。每个处理器的高速缓冲存储器具有多个端口，通过该端口可以同时读取和写入数据。操作处理器的高速缓冲存储器控制器通过使用与用于更新的端口不同的端口将高速缓冲存储器的更新数据传送到备用处理器的高速缓冲存储器。备用处理器的高速缓冲存储器控制器通过使用不同于用于更新的端口的端口将接收到的更新数据写入高速缓冲存储器。版权所有（C）2008，JPO＆INPIT

3. 发明专利

JP2001290761A BUS BRIDGE 失效
公开(公告)号：JP2001290761A
公开(公告)日：2001-10-19
申请号：JP2000103424
申请日：2000-04-05
申请人： FUJITSU LTD
发明人： TAKAHASHI MASAHIRO , YAMAGUCHI KUNIO
IPC分类号： G06F13/12 , G06F13/36 , G06F13/362 , H04L12/28
摘要： PROBLEM TO BE SOLVED: To provide a bus bridge improving the relay transfer capability. SOLUTION: This bus bridge is provided with a plurality of relay internal buses connecting a plurality of transmitting and receiving ports with each individual signal line, a receiving part receiving a 1st access request, a target specifying part specifying a target 1st relay internal bus connected to a transmitting and receiving port to be connected to the external bus of an access destination shown by the 1st access request among the plurality of relay internal buses, a deciding part deciding whether or not the 1st relay internal bus is busy, route selecting parts respectively provided in 1st to 3rd transmitting and receiving ports selecting a 2nd relay internal bus being unbusy among the plurality of relay internal buses when the 1st relay internal bus is busy, and a 1st relay requesting part making a 1st relay request in the 1st relay internal bus specified by the target specifying part or the 2nd relay internal bus selected by the route selecting part on the basis of the 1st access request.

4. 发明专利

JPH0774823A COMPOUND EXCHANGE SYSTEM 失效
公开(公告)号：JPH0774823A
公开(公告)日：1995-03-17
申请号：JP22015893
申请日：1993-09-03
申请人： FUJITSU LTD , FUJITSU KYUSHU TSUSHIN SYST KK
发明人： YAMAGUCHI KUNIO
IPC分类号： H04M3/26
摘要： PURPOSE:To enable one operator to easily confirm a cable connection. CONSTITUTION:This system is equipped with a setting means 6 which sets a control unit 2 in test mode, a test control circuit 7 which is provided to the control unit 2 and converts key input information from a command board 1 into test control information and outputs it to an interface device 3 as a substitute for control information when the test mode is set, and also converts answer information from the interface device 3 into test lump illumination information and outputs it to the command board 1 as a substitute for lamp illumination information.

5. 发明专利

JPH1124948A SYSTEM AND DEVICE FOR CONTROLLING INTERRUPTION IN MULTIPROCESSOR SYSTEM 失效
公开(公告)号：JPH1124948A
公开(公告)日：1999-01-29
申请号：JP17172397
申请日：1997-06-27
申请人： FUJITSU LTD
发明人： ICHIMURA KENJI , FUJIZONO KENJI , SUZUKI KENJI , UEMURA KAZUNORI , NAKAGAWA KIYOSHI , YAMAGUCHI KUNIO , KAWASAKI NAOKI , IGI YOZO , TAHIRA FUMIAKI , ISHIKAWA YASUHIRO
IPC分类号： G06F15/16 , G06F9/46 , G06F13/24 , G06F15/163 , G06F15/177
摘要： PROBLEM TO BE SOLVED: To obtain an interruption control system which has simple configuration and is inexpensive even when the number of processors is increased by setting a control condition to an interrupt control register and performing interruption to a processor that is an object to be controlled with the interrupt control register. SOLUTION: An interrupt controller 200 receives an interruption request from plural input-output devices and sends it to a processor 101, and a host processor sets control conditions to an interruption control register 300. The register 300 performs interruption control, e.g. over a processor 102 that is an object to be controlled. Thus, in a multiprocessor system consisting of plural processors 101 to 10n, the register 300 controls interruption requests to all of the processors 101 to 10n. Therefore, there is no need to provide an interruption controller 200 for the processors 101 to 10n, and it is possible to simplify the configuration of the multiprocessor system and to reduce costs.

6. 发明专利

JPH06177989A COMMAND TALKING RECORDING METHOD 失效
公开(公告)号：JPH06177989A
公开(公告)日：1994-06-24
申请号：JP32215692
申请日：1992-12-02
申请人： FUJITSU LTD , FUJITSU KYUSHU TSUSHIN SYST KK
发明人： YAMAGUCHI KUNIO
IPC分类号： H04M3/00 , H04M3/60
摘要： PURPOSE:To relieve a load of a board controller due to its multifunctioning by connecting an automatic recording device to a network via a command trunk. CONSTITUTION:In the command exchange system where an operation board 3 and a board control trunk 4 are connected to command trunks 6a to 6m and slave stations 7a to 7m via a network 1, the board control of an operation board 3 is implemented by a board controller 3b only and recording control by an automatic recording device 5 is implemented by the command trunk 6n. Through the constitution above, when the operation board 3 makes a command to each of the slave stations 7a to 7m, each of the slave stations 7a to 7m makes talking with the usual command trunks 6a to 6m and starts the recording device 5 to start recording of a command content. Thus, the increase in the load of the controller 3b due to multi-function of the operation board 3 through the connection of the device 5 is prevented.

7. 发明专利

JPH0581086A SYSTEM FOR STORING DATA 失效
公开(公告)号：JPH0581086A
公开(公告)日：1993-04-02
申请号：JP24123691
申请日：1991-09-20
申请人： FUJITSU LTD , FUJITSU KYUSHU TSUSHIN SYST KK
发明人： YAMAGUCHI KUNIO
IPC分类号： G06F11/34
摘要： PURPOSE:To recognize data in which area is the latest event data when successively storing data corresponding to the event in areas in the order of the event generation. CONSTITUTION:The system is provided with an event reception means 1, a data storage control means 2 successively storing the data corresponding to the event received by the event reception means 1 in areas 11, 12,...1n in the order of the event generation and overwriting the next event after stored in the final area on the first area, and a mark code storage control means 3 storing the final event identification code different from all the codes of the data corresponding to the event in the next area of the generated event storage area.

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