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1. 发明专利

JP2006259869A Multiprocessor system 审中-公开
标题翻译：多处理器系统
公开(公告)号：JP2006259869A
公开(公告)日：2006-09-28
申请号：JP2005073300
申请日：2005-03-15
申请人： Fujitsu Ltd , 富士通株式会社
发明人： YAMAGUCHI KUNIO , KAWASAKI NAOKI , NOYAMA MITSUHIRO , KAWAMOTO SHINJI
IPC分类号： G06F11/34
CPC分类号： G06F11/0784 , G06F11/0724 , G06F11/0778 , G06F11/3476
摘要： PROBLEM TO BE SOLVED: To provide a multiprocessor system capable of analyzing collaborative motion of all processors before failure when the failure occurs, with respect to the multiprocessor system where the plurality of processors 2_1-2_n are managed by a management processor 1, and accessing to a common memory 3 is controlled by a bus control device 4.
SOLUTION: The management processor 1 or the bus control device 4 provides each of the processors 2_1-1_n with time information synchronized in starting the system, and the processors 2_1-2_n respectively collect self-travel history information related to the time information. When each of the processors 2_1-2_n detects the failure, it stops the self-travel history information and notifies the other processors of the detection of failure to stop their travel history information. Each of the processors 2_1-2_n stops the collection of the self-travel history information, and stores the self-travel history information in a nonvolatile memory 13 provided besides the common memory 3.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种能够在故障发生之前分析故障之前的所有处理器的协同运动的多处理器系统，对于多处理器2_1-2_n由管理处理器1管理的多处理器系统，并且访问公共存储器3由总线控制装置4控制。解决方案：管理处理器1或总线控制装置4为每个处理器2_1-1_n提供在启动系统时同步的时间信息，并且处理器2_1-2_n分别收集与时间信息相关的自旅行历史信息。当处理器2_1-2_n中的每一个检测到故障时，它停止自行车历史信息，并通知其他处理器检测到故障以停止其旅行历史信息。每个处理器2_1-2_n停止收集自行车历史信息，并将自行车历史信息存储在除了公共存储器3之外提供的非易失性存储器13中。（C）2006，JPO＆NCIPI

2. 发明专利

JP2009104391A Memory duplex system and information processing apparatus 有权
标题翻译：存储双工系统和信息处理设备
公开(公告)号：JP2009104391A
公开(公告)日：2009-05-14
申请号：JP2007275291
申请日：2007-10-23
申请人： Fujitsu Ltd , 富士通株式会社
发明人： TAMURA RYOKO , KAWASAKI NAOKI , NOYAMA MITSUHIRO , UEMURA KAZUNORI
IPC分类号： G06F11/20 , G06F12/16 , G06F13/00
CPC分类号： H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a memory duplex system and an information processing apparatus, wherein duplex of memories can be continued even when a fault is generated in a signal line of a memory crossing bus for connecting an operation system and a standby system each other. SOLUTION: In the information processing apparatus, a system controller 3a in the operation system is provided with a protocol conversion control part 16a for converting a fault signal line into an address data configuration based on a new protocol for degenerating the fault signal line on the basis of the information of the fault signal line through which data with abnormality is transferred, and a system controller 3b in the standby system is provided with a fault signal reporting part 20b for detecting the fault signal line and reporting the information of the fault signal line to the protocol conversion control part 16a in the operation system and a protocol restoration control part 21b for restoring the fault signal line to an address data configuration held before degenerating the fault signal line on the basis of the address data configuration based on the new protocol transferred from the operation system to the standby system via a memory crossing bus 200 and the information of the fault signal line which is input from the fault signal reporting part 20b. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种存储器双工系统和信息处理装置，即使在用于连接操作系统和待机的存储器交叉总线的信号线中产生故障时，也可以继续存储器的双工相互制度。解决方案：在信息处理装置中，操作系统中的系统控制器3a设置有协议转换控制部分16a，用于将故障信号线转换为基于用于简化故障信号线的新协议的地址数据配置基于传送了异常数据的故障信号线的信息，备用系统中的系统控制器3b设置有故障信号报告部20b，用于检测故障信号线并报告故障信息信号线到操作系统中的协议转换控制部分16a，以及协议恢复控制部分21b，用于将故障信号线恢复到基于新的基于地址数据配置的故障信号线退化之前保持的地址数据配置通过存储器交叉总线200从操作系统传送到备用系统的协议和信息从故障信号报告部20b输入的故障信号线。版权所有（C）2009，JPO＆INPIT

3. 发明专利

JP2008046685A Duplex system and system switching method 审中-公开
标题翻译：双重系统和系统切换方法
公开(公告)号：JP2008046685A
公开(公告)日：2008-02-28
申请号：JP2006218898
申请日：2006-08-10
申请人： Fujitsu Ltd , 富士通株式会社
发明人： TSUKIJI HIDEKAZU , KAWASAKI NAOKI , YAMAGUCHI KUNIO , UEMURA KAZUNORI , TAMURA RIYOUKO
IPC分类号： G06F12/08 , G06F12/16
CPC分类号： G06F11/2043 , G06F11/2038 , G06F11/2097 , G06F12/0844 , G06F12/0853
摘要： PROBLEM TO BE SOLVED: To provide a duplex system and a system switching method for matching the content of cache memories loaded on both processors when update processing to the cache memories is operated by performing reading and writing through a plurality of ports for the cache memories. SOLUTION: This duplex system is configured to monitor the occurrence of a failure in any of an operational processor 20a and a standby processor 20b, and to, when a failure occurs in the operational processor, switch to the standby processor. A cache memory of each processor has a plurality of ports through which data can be simultaneously read and written. The cache memory controller of the operational processor transfers the update data for the cache memory to the cache memory of the standby processor by using a port different from the port used for updating. The cache memory controller of the standby processor writes the received update data into the cache memory by using a port different from the port used for updating. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种双工系统和系统切换方法，用于通过对多个端口进行读取和写入，来操作对高速缓冲存储器的更新处理时，将加载在两个处理器上的高速缓存存储器的内容进行匹配，缓存记忆解决方案：该双工系统被配置为监视任何操作处理器20a和备用处理器20b中的故障的发生，并且当在操作处理器中发生故障时切换到备用处理器。每个处理器的高速缓冲存储器具有多个端口，通过该端口可以同时读取和写入数据。操作处理器的高速缓冲存储器控制器通过使用与用于更新的端口不同的端口将高速缓冲存储器的更新数据传送到备用处理器的高速缓冲存储器。备用处理器的高速缓冲存储器控制器通过使用不同于用于更新的端口的端口将接收到的更新数据写入高速缓冲存储器。版权所有（C）2008，JPO＆INPIT

4. 发明专利

JP2011028448A Arbitration device, bus access arbitration program, and bus access arbitration method 有权
标题翻译：仲裁设备，总线访问仲裁程序和总线访问仲裁方法
公开(公告)号：JP2011028448A
公开(公告)日：2011-02-10
申请号：JP2009172393
申请日：2009-07-23
申请人： Fujitsu Ltd , 富士通株式会社
发明人： FURUTA MASAYUKI , NAKAGAWA KIYOSHI , MATSUMOTO KUNIHIKO , KAWASAKI NAOKI
IPC分类号： G06F13/362
摘要： PROBLEM TO BE SOLVED: To improve transfer efficiency in transferring data to a common bus.
SOLUTION: An arbitration device holds a changeover time to be required for changing-over right to access to the common bus among a plurality of DSPs, and obtains the respective phase shift values of a plurality of DSPs, based on the change-over time and temperature information of the DSPs, which is received when the temperature of the DSPs is equal to or higher than a prescribed threshold, and then, generates and outputs different clocks by each DSP through the use of a reference clock transmitted by an oscillator and the obtained phase shift values.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提高将数据传输到公共总线的传输效率。解决方案：仲裁装置保持在多个DSP之间切换访问公共总线所需要的切换时间，并且基于改变方式获得多个DSP的各个相移值，当DSP的温度等于或高于规定阈值时接收的DSP的时间和温度信息，然后通过使用由振荡器发送的参考时钟由每个DSP生成并输出不同的时钟和获得的相移值。版权所有（C）2011，JPO＆INPIT

5. 发明专利

JP2009176232A Starting device, starting method, and starting program 有权
标题翻译：启动设备，启动方法和启动程序
公开(公告)号：JP2009176232A
公开(公告)日：2009-08-06
申请号：JP2008016519
申请日：2008-01-28
申请人： Fujitsu Ltd , 富士通株式会社
发明人： HATAE SATORU , KAWASAKI NAOKI , NAKAHARA YOICHI , MATSUMOTO KAZUHISA , KAWAMOTO SHINJI , KAWAI HIROYUKI
IPC分类号： G06F9/445
摘要： PROBLEM TO BE SOLVED: To provide a starting device reducing time required for start processing by increasing access speed to a program or data required for starting in the case of restarting due to the occurrence of a fault or error during start processing of a card.
SOLUTION: The starting device 200 starting the card comprising a plurality of electronic devices, comprises a storage medium 201 storing basic data required to start the card, in a nonvolatile manner; a boot management device 202 controlling the start processing; and memories 208a-208c grouping the plurality of electronic devices for every classification of buses, connected to the boot management device 202 for every group through the buses and storing the basic data as transient data in a volatile manner. The boot management device 202 transmits the basic data to each electronic device when starting the card, transmits the same basic data as transient data to the memories 208a-208c, and carries out restart processing using the transient data.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种启动装置，通过增加对程序的访问速度或者由于在开始处理期间发生故障或错误而在重新启动的情况下开始的数据，从而减少开始处理所需的时间卡。解决方案：启动包括多个电子设备的卡的启动设备200包括以非易失性方式存储启动卡所需的基本数据的存储介质201; 控制开始处理的引导管理装置202; 以及存储器208a-208c，用于通过总线连接到每个组的引导管理装置202，并以易失性方式存储基本数据作为瞬时数据，对于每个分类的总线进行分组。启动管理装置202在启动卡时将基本数据发送到每个电子设备，将与暂时数据相同的基本数据发送到存储器208a-208c，并且使用该瞬时数据执行重新启动处理。版权所有（C）2009，JPO＆INPIT

6. 发明专利

JPH03250998A SCN NOISE ABSORPTION CIRCUIT 失效
公开(公告)号：JPH03250998A
公开(公告)日：1991-11-08
申请号：JP4797490
申请日：1990-02-28
申请人： FUJITSU LTD , FUJITSU KYUSHU TSUSHIN SYST KK
发明人： SONODA KAZUMASA , KAWASAKI NAOKI
IPC分类号： H04Q3/72
摘要： PURPOSE:To allow the SCN noise absorption circuit to flexibly cope with a change in a pulse width to be regarded as noise by providing a switch function able to set noise width desired to be absorbed optionally to the noise absorption circuit implementing the prevention of mis-detection of a line state due to scanning detection of noise by a scanner. CONSTITUTION:A noise width C desired to be absorbed is set by a switch circuit 9 or an SD point detector circuit 10. Data S0 read at present and data S1 outputted precedingly are compared by a 2nd comparator 6 as to whether or not they are equal to and when they are equal, an input data D to a memory 2 is set to 0 and the data S0 is sent as an output data by the control of a selector 7. When they are not equal, whether or not the memory input data D is equal to the setting data C is checked by a comparator 4, and when they are equal, the input data D is set to 0, and when they are not equal, an adder 5 adds number of times of checks and consecutive number information is generated. When noise is decided, the preceding data S1 is sent as a correct data and the current data S0 is not sent as an incorrect data.

7. 发明专利

JPH10254817A DMA TRANSFER CONTROL SYSTEM 失效
公开(公告)号：JPH10254817A
公开(公告)日：1998-09-25
申请号：JP5738097
申请日：1997-03-12
申请人： FUJITSU LTD
发明人： SHIGAKI YUKITAKA , KAWASAKI NAOKI , SHIBAGAKI OSAMU , NAKAMURA KAZUYUKI
IPC分类号： G06F13/28 , G06F13/36
摘要： PROBLEM TO BE SOLVED: To provide a DMA transfer control system executing fast data transfer by transferring data from any starting address at a high speed and executing read and write in parallel. SOLUTION: This control system is connected with a DMA controller 10, address buses 2A, 2B, data buses 3A and 3B. These address buses 2A, 2B, data buses 3A and 3B are connected with at least memories 4A and 4B. Then the controller 10 is provided with a switching means 11 transferring data by automatically switching to optimum transferring method such as block transfer, word transfer, fraction transfer corresponding to the situation of the transfer data at any time.

8. 发明专利

JPH02100556A NETWORK TESTER 失效
公开(公告)号：JPH02100556A
公开(公告)日：1990-04-12
申请号：JP25321088
申请日：1988-10-07
申请人： FUJITSU LTD , FUJITSU KYUSHU TSUSHIN SYST KK
发明人： TABU TAKASHI , TSUHARA KATSUYOSHI , KAWASAKI NAOKI
IPC分类号： H04M3/26
摘要： PURPOSE:To realize the perfect state simulation of a terminal by executing the test of the terminal for the subscribers circuit common control circuit of the terminal through a standardized highway during a system operating period. CONSTITUTION:Control data is outputted from a control data set signal input circuit 10, and is inputted to a time switch 16 through a multiplexer 12 during the control data period of the signal of the style of a multiframe signal to be received through an up optical highway, and the control data is stored in a storage area other than a voice exchange storage area in the time switch 16. Next, it is read out successively at timing corresponding to each subscriber's circuit, and is multiplexed in the signal of the style of the multiframe signal, and is inputted to a test data indicate signal generation circuit 34 and an electrooptic conversion circuit 36. Optical response data transmitted from the terminal is converted into the response data of an electric signal in a photoelectric conversion circuit 30, and is inputted to a data to be tested indicate signal regeneration circuit 32, and its response data can be seen by eyes through an LED, etc.

9. 发明专利

JPH1124948A SYSTEM AND DEVICE FOR CONTROLLING INTERRUPTION IN MULTIPROCESSOR SYSTEM 失效
公开(公告)号：JPH1124948A
公开(公告)日：1999-01-29
申请号：JP17172397
申请日：1997-06-27
申请人： FUJITSU LTD
发明人： ICHIMURA KENJI , FUJIZONO KENJI , SUZUKI KENJI , UEMURA KAZUNORI , NAKAGAWA KIYOSHI , YAMAGUCHI KUNIO , KAWASAKI NAOKI , IGI YOZO , TAHIRA FUMIAKI , ISHIKAWA YASUHIRO
IPC分类号： G06F15/16 , G06F9/46 , G06F13/24 , G06F15/163 , G06F15/177
摘要： PROBLEM TO BE SOLVED: To obtain an interruption control system which has simple configuration and is inexpensive even when the number of processors is increased by setting a control condition to an interrupt control register and performing interruption to a processor that is an object to be controlled with the interrupt control register. SOLUTION: An interrupt controller 200 receives an interruption request from plural input-output devices and sends it to a processor 101, and a host processor sets control conditions to an interruption control register 300. The register 300 performs interruption control, e.g. over a processor 102 that is an object to be controlled. Thus, in a multiprocessor system consisting of plural processors 101 to 10n, the register 300 controls interruption requests to all of the processors 101 to 10n. Therefore, there is no need to provide an interruption controller 200 for the processors 101 to 10n, and it is possible to simplify the configuration of the multiprocessor system and to reduce costs.

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