专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JPH1124948A SYSTEM AND DEVICE FOR CONTROLLING INTERRUPTION IN MULTIPROCESSOR SYSTEM 失效
公开(公告)号：JPH1124948A
公开(公告)日：1999-01-29
申请号：JP17172397
申请日：1997-06-27
申请人： FUJITSU LTD
发明人： ICHIMURA KENJI , FUJIZONO KENJI , SUZUKI KENJI , UEMURA KAZUNORI , NAKAGAWA KIYOSHI , YAMAGUCHI KUNIO , KAWASAKI NAOKI , IGI YOZO , TAHIRA FUMIAKI , ISHIKAWA YASUHIRO
IPC分类号： G06F15/16 , G06F9/46 , G06F13/24 , G06F15/163 , G06F15/177
摘要： PROBLEM TO BE SOLVED: To obtain an interruption control system which has simple configuration and is inexpensive even when the number of processors is increased by setting a control condition to an interrupt control register and performing interruption to a processor that is an object to be controlled with the interrupt control register. SOLUTION: An interrupt controller 200 receives an interruption request from plural input-output devices and sends it to a processor 101, and a host processor sets control conditions to an interruption control register 300. The register 300 performs interruption control, e.g. over a processor 102 that is an object to be controlled. Thus, in a multiprocessor system consisting of plural processors 101 to 10n, the register 300 controls interruption requests to all of the processors 101 to 10n. Therefore, there is no need to provide an interruption controller 200 for the processors 101 to 10n, and it is possible to simplify the configuration of the multiprocessor system and to reduce costs.

2. 发明专利

JP2009104391A Memory duplex system and information processing apparatus 有权
标题翻译：存储双工系统和信息处理设备
公开(公告)号：JP2009104391A
公开(公告)日：2009-05-14
申请号：JP2007275291
申请日：2007-10-23
申请人： Fujitsu Ltd , 富士通株式会社
发明人： TAMURA RYOKO , KAWASAKI NAOKI , NOYAMA MITSUHIRO , UEMURA KAZUNORI
IPC分类号： G06F11/20 , G06F12/16 , G06F13/00
CPC分类号： H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a memory duplex system and an information processing apparatus, wherein duplex of memories can be continued even when a fault is generated in a signal line of a memory crossing bus for connecting an operation system and a standby system each other. SOLUTION: In the information processing apparatus, a system controller 3a in the operation system is provided with a protocol conversion control part 16a for converting a fault signal line into an address data configuration based on a new protocol for degenerating the fault signal line on the basis of the information of the fault signal line through which data with abnormality is transferred, and a system controller 3b in the standby system is provided with a fault signal reporting part 20b for detecting the fault signal line and reporting the information of the fault signal line to the protocol conversion control part 16a in the operation system and a protocol restoration control part 21b for restoring the fault signal line to an address data configuration held before degenerating the fault signal line on the basis of the address data configuration based on the new protocol transferred from the operation system to the standby system via a memory crossing bus 200 and the information of the fault signal line which is input from the fault signal reporting part 20b. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种存储器双工系统和信息处理装置，即使在用于连接操作系统和待机的存储器交叉总线的信号线中产生故障时，也可以继续存储器的双工相互制度。解决方案：在信息处理装置中，操作系统中的系统控制器3a设置有协议转换控制部分16a，用于将故障信号线转换为基于用于简化故障信号线的新协议的地址数据配置基于传送了异常数据的故障信号线的信息，备用系统中的系统控制器3b设置有故障信号报告部20b，用于检测故障信号线并报告故障信息信号线到操作系统中的协议转换控制部分16a，以及协议恢复控制部分21b，用于将故障信号线恢复到基于新的基于地址数据配置的故障信号线退化之前保持的地址数据配置通过存储器交叉总线200从操作系统传送到备用系统的协议和信息从故障信号报告部20b输入的故障信号线。版权所有（C）2009，JPO＆INPIT

3. 发明专利

JP2008046685A Duplex system and system switching method 审中-公开
标题翻译：双重系统和系统切换方法
公开(公告)号：JP2008046685A
公开(公告)日：2008-02-28
申请号：JP2006218898
申请日：2006-08-10
申请人： Fujitsu Ltd , 富士通株式会社
发明人： TSUKIJI HIDEKAZU , KAWASAKI NAOKI , YAMAGUCHI KUNIO , UEMURA KAZUNORI , TAMURA RIYOUKO
IPC分类号： G06F12/08 , G06F12/16
CPC分类号： G06F11/2043 , G06F11/2038 , G06F11/2097 , G06F12/0844 , G06F12/0853
摘要： PROBLEM TO BE SOLVED: To provide a duplex system and a system switching method for matching the content of cache memories loaded on both processors when update processing to the cache memories is operated by performing reading and writing through a plurality of ports for the cache memories. SOLUTION: This duplex system is configured to monitor the occurrence of a failure in any of an operational processor 20a and a standby processor 20b, and to, when a failure occurs in the operational processor, switch to the standby processor. A cache memory of each processor has a plurality of ports through which data can be simultaneously read and written. The cache memory controller of the operational processor transfers the update data for the cache memory to the cache memory of the standby processor by using a port different from the port used for updating. The cache memory controller of the standby processor writes the received update data into the cache memory by using a port different from the port used for updating. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种双工系统和系统切换方法，用于通过对多个端口进行读取和写入，来操作对高速缓冲存储器的更新处理时，将加载在两个处理器上的高速缓存存储器的内容进行匹配，缓存记忆解决方案：该双工系统被配置为监视任何操作处理器20a和备用处理器20b中的故障的发生，并且当在操作处理器中发生故障时切换到备用处理器。每个处理器的高速缓冲存储器具有多个端口，通过该端口可以同时读取和写入数据。操作处理器的高速缓冲存储器控制器通过使用与用于更新的端口不同的端口将高速缓冲存储器的更新数据传送到备用处理器的高速缓冲存储器。备用处理器的高速缓冲存储器控制器通过使用不同于用于更新的端口的端口将接收到的更新数据写入高速缓冲存储器。版权所有（C）2008，JPO＆INPIT

4. 发明专利

JP2010220099A Monitoring device in monitoring system, subordinate device, response transmitting method, and program 有权
标题翻译：监控系统中的监控设备，子设备，响应发送方法和程序
公开(公告)号：JP2010220099A
公开(公告)日：2010-09-30
申请号：JP2009066912
申请日：2009-03-18
申请人： Fujitsu Ltd , 富士通株式会社
发明人： KUROKI TAKAHIRO , UEMURA KAZUNORI , OKAMASU TAKAYUKI
IPC分类号： H04L12/40 , H04L12/403 , H04Q9/00
摘要： PROBLEM TO BE SOLVED: To shorten the polling cycle furthermore.
SOLUTION: A monitoring device transmits a response request to a plurality of subordinate devices by multicast, and receives a response including the device identifiers and the load information from the plurality of subordinate devices. The monitoring device also updates the load information table of the plurality of subordinate devices based on the response thus received. With reference to the load information table of the monitoring device, a processing distributor distributes the information to be processed according to the load to a subordinate device of light load. The subordinate device stores the device identifiers for identifying the subordinate devices including the device. Furthermore, the subordinate device receives a request from the monitoring device, monitors the response including the device identifiers of the other subordinate devices and the load information transmitted from the other subordinate devices to the monitoring device over a bus, and transmits a response including the device identifier of the device and the load information to the monitoring device over a bus when a response including the device identifier of the subordinate device which must respond just before the device is detected.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：进一步缩短轮询周期。解决方案：监视设备通过多播向多个下属设备发送响应请求，并从多个下属设备接收包括设备标识符和负载信息的响应。监视装置还基于这样接收到的响应来更新多个从属装置的负载信息表。参照监视装置的负载信息表，处理分配器根据负载将要处理的信息分配给轻负载的下属装置。从属设备存储用于识别包括设备在内的下属设备的设备标识符。此外，从属装置接收来自监视装置的请求，通过总线监视包括其他从属装置的装置标识符和从其他下属装置发送到监视装置的负载信息的响应，并发送包括装置当包括在检测到设备之前必须响应的从属设备的设备标识符的响应时，通过总线将设备的标识符和负载信息传送到监视设备。版权所有（C）2010，JPO＆INPIT

5. 发明专利

JP2008046969A Access monitoring method and device for shared memory 审中-公开
标题翻译：访问监控方法和共享内存的设备
公开(公告)号：JP2008046969A
公开(公告)日：2008-02-28
申请号：JP2006223299
申请日：2006-08-18
申请人： Fujitsu Ltd , 富士通株式会社
发明人： URATA SHOICHI , SHIGAKI YUKITAKA , TSUKIJI HIDEKAZU , UEMURA KAZUNORI , TAMURA RIYOUKO
IPC分类号： G06F15/167 , G06F12/00
CPC分类号： G06F12/0831 , G06F9/526 , G06F12/0813
摘要： PROBLEM TO BE SOLVED: To provide an access monitoring method and an access monitoring device for a shared memory, the method and the device enabling access information from an arbitrary processor to a shared memory to be monitored irrespective of type of a multiprocessor system. SOLUTION: A bus interface part 110 of a shared memory board 100 receives a request packet RP where a processor identifier (210_1) and an acquisition request RQ1 (or a release request) of the right to access a shared memory SM are set, from an arbitrary request source processor 210_1 out of a plurality of processors 210_1 to 210_n. In response to the acquisition request RQ1 (or the release request) of the right to access the shared memory SM, the bus interface part 110 sets (or releases) the identifier (210_1) of the request source processor to (or from) the shared memory and generates an answer packet AP showing acquisition ACK1 (or release) of the access right in accordance with setting (or release) of the identifier (210_1) of the request source processor and broadcasts the answer packet to all the processors 210_1 to 210_n. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了提供用于共享存储器的访问监视方法和访问监视装置，该方法和装置使得能够监视从任意处理器到共享存储器的访问信息而不管多处理器系统的类型如何。解决方案：共享存储器板100的总线接口部分110接收请求分组RP，其中设置访问共享存储器SM的权限的处理器标识符（210_1）和获取请求RQ1（或释放请求）来自多个处理器210_1至210_n中的任意请求源处理器210_1。响应于访问共享存储器SM的获取请求RQ1（或释放请求），总线接口部分110将请求源处理器的标识符（210_1）设置为（或从）共享存储器存储器，并且根据请求源处理器的标识符（210_1）的设置（或释放）生成显示访问权限的获取ACK1（或释放）的应答包AP，并将答复包广播到所有处理器210_1至210_n。版权所有（C）2008，JPO＆INPIT

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式