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1. 发明专利

JP2008046685A Duplex system and system switching method 审中-公开
标题翻译：双重系统和系统切换方法
公开(公告)号：JP2008046685A
公开(公告)日：2008-02-28
申请号：JP2006218898
申请日：2006-08-10
申请人： Fujitsu Ltd , 富士通株式会社
发明人： TSUKIJI HIDEKAZU , KAWASAKI NAOKI , YAMAGUCHI KUNIO , UEMURA KAZUNORI , TAMURA RIYOUKO
IPC分类号： G06F12/08 , G06F12/16
CPC分类号： G06F11/2043 , G06F11/2038 , G06F11/2097 , G06F12/0844 , G06F12/0853
摘要： PROBLEM TO BE SOLVED: To provide a duplex system and a system switching method for matching the content of cache memories loaded on both processors when update processing to the cache memories is operated by performing reading and writing through a plurality of ports for the cache memories. SOLUTION: This duplex system is configured to monitor the occurrence of a failure in any of an operational processor 20a and a standby processor 20b, and to, when a failure occurs in the operational processor, switch to the standby processor. A cache memory of each processor has a plurality of ports through which data can be simultaneously read and written. The cache memory controller of the operational processor transfers the update data for the cache memory to the cache memory of the standby processor by using a port different from the port used for updating. The cache memory controller of the standby processor writes the received update data into the cache memory by using a port different from the port used for updating. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种双工系统和系统切换方法，用于通过对多个端口进行读取和写入，来操作对高速缓冲存储器的更新处理时，将加载在两个处理器上的高速缓存存储器的内容进行匹配，缓存记忆解决方案：该双工系统被配置为监视任何操作处理器20a和备用处理器20b中的故障的发生，并且当在操作处理器中发生故障时切换到备用处理器。每个处理器的高速缓冲存储器具有多个端口，通过该端口可以同时读取和写入数据。操作处理器的高速缓冲存储器控制器通过使用与用于更新的端口不同的端口将高速缓冲存储器的更新数据传送到备用处理器的高速缓冲存储器。备用处理器的高速缓冲存储器控制器通过使用不同于用于更新的端口的端口将接收到的更新数据写入高速缓冲存储器。版权所有（C）2008，JPO＆INPIT

2. 发明专利

JP2011013829A Configuration device, configuration method, and configuration program 审中-公开
标题翻译：配置设备，配置方法和配置程序
公开(公告)号：JP2011013829A
公开(公告)日：2011-01-20
申请号：JP2009155992
申请日：2009-06-30
申请人： Fujitsu Ltd , 富士通株式会社
发明人： NAGANO MANABU , UCHIBA MAKOTO , IKEMATSU HIROSHI , TSUKIJI HIDEKAZU , KOZUKI OKIHIKO , SATO YOSHITAKA , SAKASHITA YOHEI
IPC分类号： G06F1/24
摘要： PROBLEM TO BE SOLVED: To provide a configuration device for quickly and efficiently configuring an integrated circuit.SOLUTION: The configuration device includes: a circuit design information storage memory 120 for storing the circuit design information of an FPGA 140 by block units divided into fixed length; a setting circuit control device 130 for reading circuit setting information by block units, and for outputting the read circuit setting information of the block units to the FPGA 140; a write area selection part 220 for, when a setting information writable area 150 in which the circuit setting information is writable in the FPGA 140 is physically divided for each block, inputting the circuit setting information of the block units output by the setting information control device 130, and for selecting the area as the object of writing of the input circuit setting information from the divided write validating areas; and a configuration control part 210 for writing the circuit setting information of the block units output from the setting information control device 130 in the selected write object area.
摘要翻译：要解决的问题：提供用于快速高效地配置集成电路的配置装置。解决方案：配置装置包括：电路设计信息存储存储器120，用于通过分成固定长度的块单元存储FPGA 140的电路设计信息 ; 设置电路控制装置130，用于通过块单位读取电路设置信息，并将块单元的读取电路设置信息输出到FPGA 140; 写入区域选择部分220，用于在每个块物理地划分在FPGA 140中可写入电路设置信息的设置信息可写区域150时，输入由设置信息控制装置输出的块单元的电路设置信息 130，并且用于从划分的写入验证区域选择作为输入电路设置信息的写入对象的区域; 以及用于将从设置信息控制装置130输出的块单元的电路设置信息写入所选择的写入对象区域中的配置控制部分210。

3. 发明专利

JP2003284146A Exchange station 审中-公开
标题翻译：交换站
公开(公告)号：JP2003284146A
公开(公告)日：2003-10-03
申请号：JP2002083374
申请日：2002-03-25
申请人： Fujitsu Ltd , 富士通株式会社
发明人： WATANABE NORIYUKI , SHIGAKI YUKITAKA , OKAWA HIDEO , FURUTA MASAYUKI , TSUKIJI HIDEKAZU , YAMAGUCHI MASAHIRO , KINOSHITA KOICHI
IPC分类号： H04M3/42 , H04W28/26 , H04W88/14 , H04Q7/38
摘要： PROBLEM TO BE SOLVED: To provide an exchange station and a method therefore for deciding priority on the basis of a caller and a call destination without the need for a user to designate priority and being operated on the basis of the priority, a speech reservation control system having the exchange station and utilizing the method, and a mobile station for utilizing the exchange station, the method, and the speech reservation control system. SOLUTION: When the exchange station 1 receives a call from a mobile station 2 via a base station 3 and a congestion state takes place, a reservation propriety discrimination section 11b decides the propriety of reservation, a reservation propriety notice section 11a informs the mobile station 2 about the decision, when the mobile station 2 makes a reservation, a priority level setting section 12 sets a priority level on the basis of a call destination number and a caller number in the call, since a priority level processing section 14 stores reservation information to a reservation buffer section 15, the exchange station 1 can simply and quickly make reservation according to the priority by many diversified combinations of the destination numbers and caller numbers without the need for designation of the priority level by the mobile station. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：为了提供交换站和方法，因此用于基于呼叫者和呼叫目的地决定优先级，而不需要用户指定优先级并且基于优先级来操作，具有交换站并利用该方法的语音预约控制系统以及利用交换台，方法和语音预约控制系统的移动台。解决方案：当交换台1经由基站3从移动台2接收到呼叫并发生拥塞状态时，预约正确判别部分11b决定预约的适当性，预约正常通知部分11a通知移动台2关于决定，当移动站2进行预约时，优先级设定部12基于呼叫目的地号码和呼叫号码来设定优先级，因为优先级处理部14存储预约信息提供给预约缓冲部分15，交换台1可以通过目的号码和主叫号码的多种多样的组合，根据优先级简单快速地进行预约，而无需移动台指定优先级。版权所有（C）2004，JPO

4. 发明专利

JP2010226667A Integrated circuit and configuration method 有权
标题翻译：集成电路和配置方法
公开(公告)号：JP2010226667A
公开(公告)日：2010-10-07
申请号：JP2009074544
申请日：2009-03-25
申请人： Fujitsu Ltd , 富士通株式会社
发明人： SAKASHITA YOHEI , UCHIBA MAKOTO , IKEMATSU HIROSHI , TSUKIJI HIDEKAZU , KOZUKI OKIHIKO , SATO YOSHITAKA , NAGANO MANABU
IPC分类号： H03K19/173
摘要： PROBLEM TO BE SOLVED: To avoid an erroneous configuration to a field programmable gate array (FPGA) of the same kind in the same device.
SOLUTION: In an integrated circuit, as external pins for FPGA identification, four external pins are selected, that is, external pin K to external pin N of each FPGA of the same kind with the same device ID. An FPGA 1 and an FPGA 2 are identified by the status settings of the external pin K to the external pin N. For the FPGA 1 and FPGA 2, the respective configuration data includes information about "external pin K='0', external pin L='0', external pin M='0', external pin N='0'", "external pin K='0', external pin L='0', external pin M='0', external pin N='1'", as FPGA identification information. Because of this, when configuration is performed with configuration data of each FPGA, by the agreement of the FPGA identification information, it is possible to perform configuration of correct configuration data corresponding to a target FPGA.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：为了避免同一设备中相同种类的现场可编程门阵列（FPGA）的错误配置。解决方案：在集成电路中，作为FPGA标识的外部引脚，选择四个外部引脚，即同一个器件ID的同一个FPGA的外部引脚K与外部引脚N连接。 FPGA 1和FPGA 2通过外部引脚K到外部引脚N的状态设置来标识。对于FPGA 1和FPGA 2，各个配置数据包括有关“外部引脚K = 0”的信息，外部引脚 L ='0'，外部引脚M ='0'，外部引脚N ='0'，外部引脚K ='0'，外部引脚L ='0' N ='1'，作为FPGA识别信息。因此，当通过每个FPGA的配置数据执行配置时，通过FPGA识别信息的一致，可以执行与目标FPGA相对应的正确配置数据的配置。版权所有（C）2011，JPO＆INPIT

5. 发明专利

JP2008046969A Access monitoring method and device for shared memory 审中-公开
标题翻译：访问监控方法和共享内存的设备
公开(公告)号：JP2008046969A
公开(公告)日：2008-02-28
申请号：JP2006223299
申请日：2006-08-18
申请人： Fujitsu Ltd , 富士通株式会社
发明人： URATA SHOICHI , SHIGAKI YUKITAKA , TSUKIJI HIDEKAZU , UEMURA KAZUNORI , TAMURA RIYOUKO
IPC分类号： G06F15/167 , G06F12/00
CPC分类号： G06F12/0831 , G06F9/526 , G06F12/0813
摘要： PROBLEM TO BE SOLVED: To provide an access monitoring method and an access monitoring device for a shared memory, the method and the device enabling access information from an arbitrary processor to a shared memory to be monitored irrespective of type of a multiprocessor system. SOLUTION: A bus interface part 110 of a shared memory board 100 receives a request packet RP where a processor identifier (210_1) and an acquisition request RQ1 (or a release request) of the right to access a shared memory SM are set, from an arbitrary request source processor 210_1 out of a plurality of processors 210_1 to 210_n. In response to the acquisition request RQ1 (or the release request) of the right to access the shared memory SM, the bus interface part 110 sets (or releases) the identifier (210_1) of the request source processor to (or from) the shared memory and generates an answer packet AP showing acquisition ACK1 (or release) of the access right in accordance with setting (or release) of the identifier (210_1) of the request source processor and broadcasts the answer packet to all the processors 210_1 to 210_n. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了提供用于共享存储器的访问监视方法和访问监视装置，该方法和装置使得能够监视从任意处理器到共享存储器的访问信息而不管多处理器系统的类型如何。解决方案：共享存储器板100的总线接口部分110接收请求分组RP，其中设置访问共享存储器SM的权限的处理器标识符（210_1）和获取请求RQ1（或释放请求）来自多个处理器210_1至210_n中的任意请求源处理器210_1。响应于访问共享存储器SM的获取请求RQ1（或释放请求），总线接口部分110将请求源处理器的标识符（210_1）设置为（或从）共享存储器存储器，并且根据请求源处理器的标识符（210_1）的设置（或释放）生成显示访问权限的获取ACK1（或释放）的应答包AP，并将答复包广播到所有处理器210_1至210_n。版权所有（C）2008，JPO＆INPIT

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