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1. 发明专利

JP2011204941A Method of manufacturing circuit board for semiconductor element mounting, and circuit board for semiconductor element mounting 有权
标题翻译：用于半导体元件安装的电路板的制造方法和用于半导体元件安装的电路板
公开(公告)号：JP2011204941A
公开(公告)日：2011-10-13
申请号：JP2010071330
申请日：2010-03-26
申请人： Fujitsu Ltd , 富士通株式会社
发明人： KURASHINA MAMORU , MIZUTANI DAISUKE , FUKUMORI HIROMASA , KOIDE MASATERU
IPC分类号： H01L21/60 , H05K3/34
CPC分类号： H01L2224/16225 , H01L2924/3511
摘要： PROBLEM TO BE SOLVED: To provide a circuit board for mounting semiconductor elements in which when a semiconductor element such as an SLI having ball-shaped solder bumps is mounted on a package substrate having preliminary solders on electrodes, both are mounted with high reliability by absorbing variance in height and a relative position shift of each preliminary solder due to warpage of the substrate, and to provide a method of manufacturing the circuit board for semiconductor element mounting.SOLUTION: On the package substrate 1, columnar preliminary solders (solder structures 4 for connection formed by die pressing) each having a concave region which is hollowed at a center part on a top surface as compared with a peripheral part are formed by press processing using a die 5 for tip parts, and the LSI is thereby mounted by flip-chip bonding the solder bumps. The outer peripheral of the tip part of each preliminary solder is made higher than the center part to increase the flexibility of contacting and joining between the solder bump and preliminary solder in horizontal and vertical directions, thereby suppressing a connection defect due to warpage of the substrate.
摘要翻译：要解决的问题：提供一种用于安装半导体元件的电路板，其中当诸如具有球形焊料凸块的SLI等半导体元件安装在具有电极上的初步焊料的封装基板上时，通过吸收并且提供一种制造用于半导体元件安装的电路板的方法。解决方案：在封装基板1上，将柱状初步焊料（焊料结构4用于与周边部相比，在顶面的中央部分具有中空的凹部区域通过模压形成的连接形成为通过使用用于尖端部的模具5的冲压加工而形成的，芯片焊接焊点。使每个预焊料的前端部的外周部比中心部高，以增加焊料凸块与预备焊料在水平和垂直方向的接触和接合的灵活性，从而抑制由于基板的翘曲引起的连接缺陷。

2. 发明专利

JP2006253189A Multilayer substrate and manufacturing method thereof 审中-公开
标题翻译：多层基板及其制造方法
公开(公告)号：JP2006253189A
公开(公告)日：2006-09-21
申请号：JP2005063751
申请日：2005-03-08
申请人： Fujitsu Ltd , 富士通株式会社
发明人： KURASHINA MAMORU , MIZUTANI DAISUKE
IPC分类号： H05K3/46 , B05D5/12 , H05K3/40
摘要： PROBLEM TO BE SOLVED: To provide a multilayer substrate capable of reducing stress on vias while avoiding elongation of a signal transmission distance due to change of the vias, resulting in high connection reliability of vias, and to provide a manufacturing method thereof. SOLUTION: A film easily etched with a desmear liquid is formed as an insulation film 6, and a film hardly etched with the desmear liquid is formed as an insulating film 7. A via hole 8 is formed on the insulating films 6, 7 by laser irradiation. The cross section of the via hole 8 is tapered by the influence of the laser irradiation. In eliminating the smear generated in forming the via hole 8 using the desmear liquid, since a portion exposed on the via hole 8 of the insulating film 6 is also etched, the side face of the insulating film 6 also retreats and the via hole 8 becomes drum shaped. After that, a Cu seed layer is formed in the via hole 8 by a non-electrolytic plating method. Then the insulating films 6, 7 are cured. Subsequently, a Cu via 9 is embedded in the via hole 8 by an electrolytic plating method. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种能够减小通孔上的应力的多层基板，同时避免由于通孔的变化导致的信号传输距离的延长，导致通孔的高连接可靠性，并提供其制造方法。解决方案：作为绝缘膜6，形成容易用去污液蚀刻的薄膜作为绝缘膜7，绝缘膜7上形成有几乎不被蚀刻液蚀刻的薄膜。在绝缘薄膜6上形成通孔8， 7通过激光照射。通孔8的横截面通过激光照射的影响而变细。为了消除使用去污液形成通孔8所产生的污迹，由于也蚀刻了在绝缘膜6的通孔8上暴露的部分，所以绝缘膜6的侧面也退缩，通路孔8变成鼓形。之后，通过非电解电镀法在通孔8中形成Cu籽晶层。然后使绝缘膜6,7固化。随后，通过电解电镀法将Cu通孔9嵌入通孔8中。版权所有（C）2006，JPO＆NCIPI

3. 发明专利

JP2004247483A Method of manufacturing circuit board 审中-公开
公开(公告)号：JP2004247483A
公开(公告)日：2004-09-02
申请号：JP2003035262
申请日：2003-02-13
申请人： Fujitsu Ltd , Toagosei Co Ltd , 富士通株式会社 , 東亞合成株式会社
发明人： KURASHINA MAMORU , COORAY F N , TAKEI MASAO
IPC分类号： H05K3/28 , H01L23/12 , H05K3/34
CPC分类号： H01L2224/16225
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a circuit board by which an insulating passivation film formed with an opening to expose a bump electrode can be formed relatively easily and at low cost. SOLUTION: First, a substrate 10 formed with the bump electrode 12 and an interconnection 13 is prepared. Next, an insulating resin film is laminated on the substrate 10 to form the insulating passivation film 15. Then, the substrate 10 is hot-pressed between two flat plates, thereby making the insulating passivation film 15 thin on the bump electrode 12 and thick on the other portions. Thereafter, the insulating passivation film 15 is dry-etched to form the opening to expose the bump electrode 12. The interconnection 13 is covered and protected by a remaining part of the insulating passivation film 15. COPYRIGHT: (C)2004,JPO&NCIPI

4. 发明专利

JP2004158744A Selective insulating method and mounting substrate provided with through via 有权
标题翻译：选择性绝缘方法和通过通过提供的安装基板
公开(公告)号：JP2004158744A
公开(公告)日：2004-06-03
申请号：JP2002324760
申请日：2002-11-08
申请人： Fujitsu Ltd , 富士通株式会社
发明人： KURASHINA MAMORU , YAMAGISHI YASUO
IPC分类号： H01L23/32
摘要： PROBLEM TO BE SOLVED: To form an insulating film on the sidewall of a through via hole formed in a substrate with low conductivity with high accuracy in a selective insulating method, and a mounting substrate formed with the through via.
SOLUTION: A selective exposed part is formed on the conductive substrate 1 having conductivity of at least ≥10
-8 S/cm(siemens/centimeter) and ≤10
5 S/cm. Thereafter, either a charged insulating material or its precursor is electrically electrodeposited on the exposed surface of the selective exposed part.
COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：在选择性绝缘方法中以高精度形成在基板上的通孔形成的通孔的侧壁上形成绝缘膜，以及形成有通孔的安装基板。解决方案：选择性暴露部分形成在导电性基体1上，导电性基材1的导电率至少≥10×SP> -8S / cm（西门子/厘米）和≤10 5 S /厘米。此后，带电的绝缘材料或其前体电沉积在选择性暴露部分的暴露表面上。版权所有（C）2004，JPO

5. 发明专利

JP2014022640A Wiring board, method of manufacturing the same, electronic apparatus, and method of manufacturing the same 有权
标题翻译：接线板及其制造方法，电子设备及其制造方法
公开(公告)号：JP2014022640A
公开(公告)日：2014-02-03
申请号：JP2012161495
申请日：2012-07-20
申请人： Fujitsu Ltd , 富士通株式会社
发明人： FUKUMORI HIROMASA , MIZUTANI DAISUKE , KURASHINA MAMORU
IPC分类号： H01L23/12
CPC分类号： H01L21/76898 , H01L21/76877 , H01L23/481 , H01L23/49811 , H01L23/49822 , H01L23/49827 , H01L23/66 , H01L24/05 , H01L24/13 , H01L2223/6616 , H01L2224/0401 , H01L2224/05647 , H01L2224/13611 , H01L2224/13639 , H01L2224/16
摘要： PROBLEM TO BE SOLVED: To suppress a change in characteristic impedance at a joint part between substrates.SOLUTION: A wiring board includes: a substrate; an insulating part formed on the substrate and having a through hole; an electrode formed on the substrate and provided in the through hole; and a conductive part joined to the electrode and provided in the through hole. The through hole expands toward a direction away from the substrate. The conductive part covers the entire upper surface of the electrode and expands toward a direction away from the substrate.
摘要翻译：要解决的问题：抑制基板之间的接合部处的特性阻抗的变化。解决方案：布线板包括：基板; 绝缘部，形成在所述基板上并具有通孔; 形成在基板上并设置在通孔中的电极; 以及连接到电极并设置在通孔中的导电部分。通孔朝远离基板的方向膨胀。导电部分覆盖电极的整个上表面并且朝远离基板的方向膨胀。

6. 发明专利

JP2013041991A Multilayer circuit board, manufacturing method of the same and semiconductor device 审中-公开
标题翻译：多层电路板及其半导体器件的制造方法
公开(公告)号：JP2013041991A
公开(公告)日：2013-02-28
申请号：JP2011177922
申请日：2011-08-16
申请人： Fujitsu Ltd , 富士通株式会社
发明人： FUKUMORI HIROMASA , MIZUTANI DAISUKE , KURASHINA MAMORU
IPC分类号： H05K3/46 , H01L21/60 , H01L23/12
摘要： PROBLEM TO BE SOLVED: To provide a multilayer circuit board, a manufacturing method of the same and a semiconductor device, which achieve impedance matching in vicinity to an electrode terminal exposed on a board surface.SOLUTION: A multilayer circuit board comprises: a multilayer substrate in which a plurality of insulation layers and a plurality of conductor layers are alternately laminated one by one; a truncated cone-shaped via conductor formed on one principal surface side of the multilayer substrate with a diameter increasing towards the principal surface from the inside of the multilayer substrate; and a ground electrode having a longitudinal section which is formed coaxially with the truncated cone-shaped via conductor through an insulation layer and has a tapered part.
摘要翻译：要解决的问题：提供一种多层电路板，其制造方法和半导体器件，其实现了暴露在电路板表面上的电极端子附近的阻抗匹配。解决方案：多层电路板包括：多层基板，其中多个绝缘层和多个导体层逐个交替层叠; 形成在所述多层基板的一个主表面侧的截面锥形通孔导体，所述多层基板的直径从所述多层基板的内部朝向所述主表面增加; 以及具有纵截面的接地电极，所述纵向截面通过绝缘层与所述截头圆锥形通孔导体同轴形成，并具有锥形部分。版权所有（C）2013，JPO＆INPIT

7. 发明专利

JP2013033853A Mounting board, semiconductor device, and electronic apparatus 有权
标题翻译：安装板，半导体器件和电子设备
公开(公告)号：JP2013033853A
公开(公告)日：2013-02-14
申请号：JP2011169171
申请日：2011-08-02
申请人： Fujitsu Ltd , 富士通株式会社
发明人： KURASHINA MAMORU , MIZUTANI DAISUKE , FUKUMORI HIROMASA
IPC分类号： H01L23/12
摘要： PROBLEM TO BE SOLVED: To improve mounting reliability by ensuring the flatness of a mounting board, in the mounting board, a semiconductor device, and an electronic apparatus.SOLUTION: A mounting board includes a circuit board and a reinforcement member that is fixed to the circuit board by mechanical fixing means and bonding means, has a larger stiffness than the circuit board and has an opening at a position corresponding to a mounting area for a semiconductor element. The mechanical fixing means fixes the reinforcement member at four corners of the circuit board. The bonding means bonds the reinforcement member to the circuit board at four positions whose centers are located inside the sides connecting the mechanical fixing means at the four corners and are symmetrical with respect to the center of the circuit board.
摘要翻译：要解决的问题：通过确保安装板，安装板，半导体器件和电子设备的平坦度来提高安装可靠性。解决方案：安装板包括电路板和通过机械固定装置和接合装置固定到电路板的加强构件，具有比电路板更大的刚度，并且在对应于安装的位置处具有开口半导体元件的面积。机械固定装置将加强件固定在电路板的四个角处。接合装置将加强构件连接到电路板，其中心位于四个角处连接机械固定装置的侧面的四个位置处，并且相对于电路板的中心对称。版权所有（C）2013，JPO＆INPIT

8. 发明专利

JP2011146451A Electronic device and manufacturing method for the same 有权
标题翻译：电子设备及其制造方法
公开(公告)号：JP2011146451A
公开(公告)日：2011-07-28
申请号：JP2010004528
申请日：2010-01-13
申请人： Fujitsu Ltd , 富士通株式会社
发明人： KURASHINA MAMORU , MIZUTANI DAISUKE , FUKUMORI HIROMASA , FUKUSONO KENJI
IPC分类号： H01L23/12 , H01L23/32 , H01L23/36
CPC分类号： H01L2224/16225 , H01L2224/32245 , H01L2224/73253 , H01L2924/15311
摘要： PROBLEM TO BE SOLVED: To provide a high reliability electronic device by suppressing deformations of a wiring board.
SOLUTION: A stiffener 12, arranged on a package substrate 11, is provided with a protrusion 12b protruding to a side opposite to the side of the package substrate 11 so as to surround opening 12a of the stiffener. A semiconductor chip 13 is arranged on the package substrate 11 arranged with such a stiffener 12. The stiffener 12, provided with the protrusion 12b, is used in an electronic device, thereby suppressing deformation of the package substrate 11.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：通过抑制布线板的变形来提供高可靠性的电子设备。解决方案：设置在封装基板11上的加强件12设置有突出部12b，突出部12b突出到与封装基板11的侧面相反的一侧，以便包围加强件的开口12a。半导体芯片13布置在具有这种加强件12的封装基板11上。设置有突起12b的加强件12用于电子设备，从而抑制封装基板11的变形。版权所有（ C）2011，JPO＆INPIT

9. 发明专利

JP2007256345A Resin pattern forming method 审中-公开
标题翻译：树脂图案形成方法
公开(公告)号：JP2007256345A
公开(公告)日：2007-10-04
申请号：JP2006077175
申请日：2006-03-20
申请人： Fujitsu Ltd , 富士通株式会社
发明人： KURASHINA MAMORU
IPC分类号： G03F7/004 , G03F7/008 , G03F7/016 , G03F7/075 , G03F7/11 , H01L21/027
摘要： PROBLEM TO BE SOLVED: To provide a resin pattern forming method by which swelling and deterioration of a resin pattern in a production process can be suppressed, a usable resin can be selected from a wider range, and a fine high-definition resin pattern can be efficiently formed in a simple and easy way at a low cost.
SOLUTION: The resin pattern forming method includes: a resin fixing layer forming step of forming on a substrate a resin fixing layer comprising a compound for resin fixing having at least a bonding group which has capability of bonding to the above resin when irradiated with light and a functional group capable of bonding to a surface of the substrate; a resin layer forming step of forming a resin layer comprising the resin on the resin fixing layer; a latent image forming step of forming a latent image by imagewise irradiating the resin layer with light to bond the resin fixing layer to the resin layer in the light irradiated area; and a development step of developing a resin pattern by peeling and removing the resin layer in the light unirradiated area by physical stimulation.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：待解决的问题：为了提供可以抑制生产过程中的树脂图案的膨胀和劣化的树脂图案形成方法，可以从更宽的范围内选择可用的树脂，并且可以使用精细的高分辨树脂可以以简单和容易的方式以低成本有效地形成图案。解决方案：树脂图案形成方法包括：树脂固定层形成步骤，在基板上形成树脂固定层，该树脂固定层包括至少具有在照射时具有与上述树脂结合能力的接合基团的树脂固定化合物具有光和能够结合到基底的表面的官能团; 树脂层形成步骤，在树脂固定层上形成包含树脂的树脂层; 潜像形成步骤，通过用光对所述树脂层进行成像照射来形成潜像，以将所述树脂固定层粘合到所述光照射区域中的所述树脂层; 以及通过物理刺激剥离和去除光未照射区域中的树脂层来显影树脂图案的显影步骤。版权所有（C）2008，JPO＆INPIT

10. 发明专利

JP2006339440A Substrate with through-via and its manufacturing method 审中-公开
标题翻译：具有通过威胁的基板及其制造方法
公开(公告)号：JP2006339440A
公开(公告)日：2006-12-14
申请号：JP2005162748
申请日：2005-06-02
申请人： Fujitsu Ltd , 富士通株式会社
发明人： KURASHINA MAMORU , ABE TOMOYUKI
IPC分类号： H05K1/11 , H05K3/40 , H05K3/42 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To manufacture a substrate having a low thermal expansion coefficient in which a through-via is formed by filling an insulated through-hole with a conductive material after forming the through-hole without damaging substrate characteristics, with further reduced number of processes and at lower manufacturing costs regarding the substrate with the through-vias and its manufacturing method. SOLUTION: The substrate with the through-vias includes a plurality of resin insulating layers 1 and base materials 2 that are alternately laminated, a clearance hole penetrating the resin insulating layers 1 and the base materials 2, a through-via insulating film 1A formed to the inner wall face of the clearance hole with a part of the resin insulating layers 1, and the through-via 5 formed by filling the through-hole surrounded by the through-via insulating film. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了制造具有低热膨胀系数的基板，其中通过在形成通孔之后用导电材料填充绝缘的通孔而形成通孔，而不损坏基板特性，进一步减少了工艺数量，并降低了具有贯通孔的基板及其制造方法的制造成本。解决方案：具有贯通孔的基板包括交替层叠的多个树脂绝缘层1和基材2，贯穿树脂绝缘层1和基材2的间隙孔，通孔绝缘膜 1A形成于间隙孔的内壁面与树脂绝缘层1的一部分，通孔5通过填充由通孔绝缘膜包围的通孔而形成。版权所有（C）2007，JPO＆INPIT

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