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1. 发明专利

JP2014183057A Semiconductor device manufacturing method and semiconductor mounting substrate 有权
标题翻译：半导体器件制造方法和半导体安装基板
公开(公告)号：JP2014183057A
公开(公告)日：2014-09-29
申请号：JP2013054525
申请日：2013-03-18
申请人： Fujitsu Ltd , 富士通株式会社
发明人： KURASHINA MAMORU , MIZUTANI DAISUKE
IPC分类号： H01L23/32 , H01L21/60 , H01L23/12
CPC分类号： H05K1/0271 , H01L21/4853 , H01L21/76877 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49833 , H01L23/49894 , H01L24/81 , H01L2224/0401 , H01L2224/08235 , H01L2224/131 , H01L2224/16235 , H01L2224/81191 , H01L2224/8121 , H01L2224/81815 , H01L2924/1306 , H01L2924/351 , H05K1/0298 , H05K1/0326 , H05K1/0346 , H05K1/115 , H05K2201/0154 , H05K2201/09136 , H05K2201/10734 , H01L2924/00 , H01L2924/014
摘要： PROBLEM TO BE SOLVED: To provide a connection method of inhibiting an unconnected state between an electrode of a semiconductor substrate and a substrate electrode for mounting the semiconductor substrate.SOLUTION: A semiconductor device manufacturing method comprises: a first process of mounting on a first substrate on which a plurality of distribution lines and a plurality of first electrodes connected to the plurality of distribution lines are formed, respectively, a second substrate on which a plurality of through holes corresponding to the plurality of first electrodes and a plurality of relay members each formed by a solder and protrudes on both sides of one through hole are provided in a manner such that the plurality of first electrodes and the plurality of through holes overlap each other in planar view; a second process of melting the plurality of relay members to connect the plurality of relay members with the plurality of first electrodes after the first process; and a third process of arranging a semiconductor substrate on which a plurality of second electrodes corresponding to the plurality of first electrodes are formed on the side opposite to the first substrate across the second substrate to connect the plurality of first electrodes with the plurality of second electrodes via the plurality of relay members after the second process.
摘要翻译：要解决的问题：提供一种抑制半导体衬底的电极和用于安装半导体衬底的衬底电极之间的未连接状态的连接方法。解决方案：半导体器件制造方法包括：第一工艺，其安装在第一衬底上分别形成多个分配线和与多个分配线连接的多个第一电极，第二基板上分别形成有与多个第一电极对应的多个通孔和多个中继部件通过焊料并在一个通孔的两侧突出的方式设置成使得多个第一电极和多个通孔在平面视图中彼此重叠; 在所述第一处理之后，熔化所述多个中继构件以将所述多个中继构件与所述多个第一电极连接的第二工序; 以及配置半导体衬底的第三工序，在所述半导体衬底上配置有与所述多个第一电极对应的多个第二电极，所述半导体衬底在与所述第一衬底相对的一侧上跨越所述第二衬底形成，以将所述多个第一电极与所述多个第二电极经过第二处理后的多个中继部件。

2. 发明专利

JP2012204699A Circuit board, and method of manufacturing the same, and semiconductor device 有权
标题翻译：电路板及其制造方法和半导体器件
公开(公告)号：JP2012204699A
公开(公告)日：2012-10-22
申请号：JP2011069024
申请日：2011-03-26
申请人： Fujitsu Ltd , 富士通株式会社
发明人： MIZUTANI DAISUKE
IPC分类号： H05K3/46 , H01L23/12
摘要： PROBLEM TO BE SOLVED: To provide a component built-in circuit board being flat and having a high rigidity.SOLUTION: A circuit board 120 has a core member 20 having: a first copper foil 22d tightly adhered to a lower surface of a resin sheet 22b and having an opening 22d-1 immediately under a mounting region 60 where a semiconductor device is mounted; a via hole 28 formed in the opening 22d-1 and penetrating through the resin sheet 22b; an electronic component 24 connected with a lower end of the via 28 and arranged on the lower surface of the resin sheet 22b; a mold resin compact 25 tightly adhered to the lower surface of the resin sheet 22b and incorporating the electronic component 24; a core plate 21 provided with a through-hole 21a through which the mold resin compact 25 is inserted, and having a rigidity; and an adhesive material 26 adhering the core plate 21 into whose through-hole 21a the mold resin compact 25 is inserted to the lower surface of the resin seat 22b.
摘要翻译：要解决的问题：提供一种扁平且具有高刚性的内置电路板。解决方案：电路板120具有芯构件20，芯构件20具有：紧密地粘附到树脂片22b的下表面上的第一铜箔22d，并且在紧固在半导体器件为安装区域60的安装区域60下方具有开口22d-1 安装; 形成在开口22d-1中并穿过树脂片22b的通孔28; 与通孔28的下端连接并布置在树脂片22b的下表面上的电子部件24; 模制树脂紧固件25紧密地粘附到树脂薄片22b的下表面并且结合有电子部件24; 芯板21，其设置有插入模塑树脂压块25的通孔21a，并具有刚性; 以及粘合剂材料26，将芯板21粘合到其树脂制座体22b的下表面插入模具树脂压块25的通孔21a中。版权所有（C）2013，JPO＆INPIT

3. 发明专利

JP2011086820A Multi-chip module 有权
标题翻译：多芯片模块
公开(公告)号：JP2011086820A
公开(公告)日：2011-04-28
申请号：JP2009239489
申请日：2009-10-16
申请人： Fujitsu Ltd , Fujitsu Semiconductor Ltd , 富士通セミコンダクター株式会社 , 富士通株式会社
发明人： KOIDE MASATERU , MIZUTANI DAISUKE , INOUE AIICHIRO , YAMASHITA HIDEO , YAMAZAKI IWAO , KATO MASAYUKI , UENO SEIJI , IMAMURA KAZUYUKI
IPC分类号： H01L25/04 , H01L23/52 , H01L25/18
CPC分类号： H01L23/49827 , H01L23/49822 , H01L23/66 , H01L24/16 , H01L25/0655 , H01L2224/131 , H01L2224/16235 , H01L2224/73253 , H01L2924/0001 , H01L2924/01078 , H01L2924/10253 , H01L2924/014 , H01L2224/13099 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To shorten the wiring lengths among LSI chips in a multi-chip module. SOLUTION: A plurality of LSI chips 30A-30D are arranged on a silicon interposer 20 with a wiring pattern 26a and each of the LSI chips is connected to the other LSI chips via the wiring pattern 26a, and the plurality of LSI chips and a base substrate 10 are electrically connected to each other via a portion excluding the wiring pattern 26a. In this case, the silicon interposer 20 can be manufactured separately from the base substrate, thereby making a wiring pattern into a micropattern. As a result, the wiring pattern can be made short, and wiring lengths among LSI chips can be shortened also. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：缩短多芯片模块中的LSI芯片之间的布线长度。解决方案：多个LSI芯片30A-30D布置在具有布线图案26a的硅插入件20上，并且每个LSI芯片经由布线图案26a连接到其它LSI芯片，并且多个LSI芯片并且基底基板10经由除布线图案26a之外的部分彼此电连接。在这种情况下，可以与基底基板分开制造硅插入件20，从而将布线图案形成为微图案。结果，可以缩短布线图案，并且也可以缩短LSI芯片之间的布线长度。版权所有（C）2011，JPO＆INPIT

4. 发明专利

JP2011082221A Interconnect board, printed circuit board unit, and method of manufacturing interconnect board 有权
标题翻译：互连板，印刷电路板单元及制造互连板的方法
公开(公告)号：JP2011082221A
公开(公告)日：2011-04-21
申请号：JP2009230912
申请日：2009-10-02
申请人： Fujitsu Ltd , 富士通株式会社
发明人： KOIDE MASATERU , MIZUTANI DAISUKE
IPC分类号： H01L23/32 , H05K1/11 , H05K1/14
CPC分类号： H05K1/141 , H01L23/142 , H01L23/49827 , H01L2224/16225 , H01L2224/16227 , H01L2224/73204 , H01L2924/00014 , H01L2924/15311 , H05K3/445 , H05K2201/10378 , H05K2201/10477 , H01L2224/0401
摘要： PROBLEM TO BE SOLVED: To mount a semiconductor element package on a circuit board without increasing a cost and without degrading electric performances of the semiconductor element package and the circuit board.
SOLUTION: An interconnect board 20 interposed between a first circuit board 10 and a second circuit board 30 mounts the first circuit board 10 to the second circuit board 30. A metal plate 22 involved functions as a power supply layer or a ground layer electrically connected to a power supply terminal or a ground terminal of each of the first circuit board 10 and the second circuit board 30 through a first connection terminal 23-1 and a second connection terminal 23-2. A metal pile 24 electrically connects a signal terminal of the first circuit board 10 to the corresponding signal terminal of the second circuit board 30. The interconnect board 20 electrically connects the first circuit board 10 to the second circuit board 30, and an insulating layer 21 and the metal plate 22 function as a stiffener. Accordingly, stress caused due to deflection and warpage of the first circuit board 10 can be suppressed.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：将半导体元件封装安装在电路板上，而不增加成本并且不降低半导体元件封装和电路板的电气性能。插入在第一电路板10和第二电路板30之间的互连板20将第一电路板10安装到第二电路板30.金属板22用作电源层或接地层通过第一连接端子23-1和第二连接端子23-2电连接到第一电路板10和第二电路板30中的每一个的电源端子或接地端子。金属堆24将第一电路板10的信号端子与第二电路板30的对应的信号端子电连接。互连板20将第一电路板10电连接到第二电路板30，绝缘层21 并且金属板22用作加强件。因此，可以抑制由于第一电路板10的偏转和翘曲引起的应力。版权所有（C）2011，JPO＆INPIT

5. 发明专利

JP2009129921A Manufacturing method of printed board with built-in component, and semiconductor device 审中-公开
标题翻译：具有内置元件的印刷电路板的制造方法和半导体器件
公开(公告)号：JP2009129921A
公开(公告)日：2009-06-11
申请号：JP2007299633
申请日：2007-11-19
申请人： Fujitsu Ltd , 富士通株式会社
发明人： TANI MOTOAKI , MIZUTANI DAISUKE
IPC分类号： H05K3/46 , H01L23/12
CPC分类号： H01L2224/19 , H01L2224/73267 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To thin the thickness of a built-in electronic component to be mounted on a printed board with built-in component without damaging the built-in electronic component so as to thin the thickness of the printed board with built-in component.
SOLUTION: The manufacturing method of the printed board with built-in component includes: a process of mounting the built-in electronic component 1 face-down on an internal-layer printed board 2; a process of covering a portion of at least a side surface of the electronic component 1 with an insulating material 4 and curing it; a process of grinding the electronic component 1 and insulating material 3 thin to form the component built-in internal-layer printed board 22; and a process of stacking prepregs 43 for coating on both top and reverse surfaces of the component built-in internal-layer printed board 2 and curing them.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了使内置组件的内置电子部件的厚度变薄，而不会损坏内置的电子部件，以便使印刷电路板的厚度变薄内置组件。解决方案：具有内置部件的印刷电路板的制造方法包括：将内置电子部件1面朝下地安装在内层印刷电路板2上的工序; 用绝缘材料4覆盖电子部件1的至少侧面的一部分的一部分，使其固化的工序; 将电子部件1和绝缘材料3细磨以形成内置内层印刷电路板22的工序; 以及堆叠用于在内置内置印刷电路板2的上表面和反面上涂布并固化它们的预浸料43的工艺。版权所有（C）2009，JPO＆INPIT

6. 发明专利

JP2008235408A Differential transmission circuit board and manufacturing method thereof 审中-公开
标题翻译：差分传输电路板及其制造方法
公开(公告)号：JP2008235408A
公开(公告)日：2008-10-02
申请号：JP2007070125
申请日：2007-03-19
申请人： Fujitsu Ltd , 富士通株式会社
发明人： MIZUTANI DAISUKE
IPC分类号： H05K3/04 , H05K3/22
摘要： PROBLEM TO BE SOLVED: To provide a circuit board structure guaranteeing stable differential transmission characteristics, regarding a manufacturing method for a differential transmission circuit board and a differential transmission circuit board manufactured therewith.
SOLUTION: By having gaps 4 formed to a conductive layer 2 that is formed on an insulating layer 1 machined, two adjacent wirings 5 and 6 are formed.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：关于用于差分传输电路板的制造方法和由其制造的差分传输电路板，提供保证稳定的差分传输特性的电路板结构。解决方案：通过对形成在被加工的绝缘层1上的导电层2形成间隙4，形成两个相邻布线5和6。版权所有（C）2009，JPO＆INPIT

7. 发明专利

JP2007335652A Semiconductor device, circuit board, and their manufacturing methods 审中-公开
标题翻译：半导体器件，电路板及其制造方法
公开(公告)号：JP2007335652A
公开(公告)日：2007-12-27
申请号：JP2006166135
申请日：2006-06-15
申请人： Fujitsu Ltd , 富士通株式会社
发明人： AKAMATSU TOSHIYA , SAKUYAMA SEIKI , MIZUTANI DAISUKE
IPC分类号： H05K3/34 , H01L21/60 , H01L23/12
CPC分类号： H01L2224/16225
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device subjected to highly reliable packaging, a circuit board capable of its packaging, and their manufacturing methods. SOLUTION: In a semiconductor device 1 undergoing packaging by a ball grid array, a pattern electrode constituted of a Cu film 21 is formed on a resin substrate 20. An opening 23 is formed which penetrates the surface of a solder resist 22 formed on a resin substrate 20 to the surface of the Cu film 21. A solder ball 12 joined with an electrode pad 11 of a semiconductor package 10 and the Cu film 21 are electrically connected by preliminary solder 24 filled in the opening 23. According to such a semiconductor device 1, it is possible to relax stress concentratedly generated when the solder ball 12 and the Cu film 21 are directly joined with each other, and thereby to restrict any crack generated at joined portions. It is therefore possible to obtain a highly reliable semiconductor device. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供经受高可靠性封装的半导体器件，能够进行封装的电路板及其制造方法。解决方案：在通过球栅阵列进行封装的半导体器件1中，在树脂基板20上形成由Cu膜21构成的图案电极。形成开口23，其穿过形成的阻焊剂22的表面在树脂基板20上的铜膜21的表面。与半导体封装10的电极焊盘11和Cu膜21接合的焊球12通过填充在开口23中的预焊料24电连接。根据这样半导体器件1，可以缓和焊球12和Cu膜21彼此直接接合时集中产生的应力，从而限制在接合部处产生的任何裂纹。因此，可以获得高可靠性的半导体器件。版权所有（C）2008，JPO＆INPIT

8. 发明专利

JP2007005561A Electronic device having double sided mounting circuit substrate with built-in capacitor 有权
标题翻译：具有内置电容器的双面安装电路基板的电子设备
公开(公告)号：JP2007005561A
公开(公告)日：2007-01-11
申请号：JP2005183815
申请日：2005-06-23
申请人： Fujitsu Ltd , 富士通株式会社
发明人： MIZUTANI DAISUKE
IPC分类号： H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L2224/16
摘要： PROBLEM TO BE SOLVED: To provide a mounting structure which raises mounting density of a semiconductor element and enables a capacitor to be disposed near the semiconductor element in the double sided mounting circuit substrate unit. SOLUTION: The double sided mounting circuit substrate unit 10 has two circuit substrates 12 with a surface for mounting the semiconductor element 11 and a surface exposing a ground layer 14, and a plate-like capacitor which has a power supply layer formed held between two dielectric layers and exposes the ground layer 14 insulated from the power supply layer by the dielectric layer to a surface. The two circuit substrates and the plate-like capacitor are electrically connected, and the plate-like capacitor is inserted between the two circuit substrates disposed such that the ground layers thereof are opposed. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种提高半导体元件的安装密度并使得电容器能够设置在双面安装电路基板单元中的半导体元件附近的安装结构。
解决方案：双面安装电路基板单元10具有两个电路基板12，其具有用于安装半导体元件11的表面和暴露接地层14的表面，以及具有形成保持的电源层的板状电容器在两个电介质层之间并且通过电介质层将与电源层绝缘的接地层14暴露于表面。两个电路基板和板状电容器电连接，并且板状电容器插入设置成使其接地层相对的两个电路基板之间。版权所有（C）2007，JPO＆INPIT

9. 发明专利

JP2006261557A Substrate for package 有权
标题翻译：包装基材
公开(公告)号：JP2006261557A
公开(公告)日：2006-09-28
申请号：JP2005079752
申请日：2005-03-18
申请人： Fujitsu Ltd , 富士通株式会社
发明人： HAYASHI NOBUYUKI , MIZUTANI DAISUKE
IPC分类号： H01L23/12 , H01P5/08
CPC分类号： H01L2224/16225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a substrate for a high-frequency semiconductor package which is hardly affected by parasitic inductance or parasitic capacity, accordingly exhibits small transmission loss, and exhibits a high degree of electromagnetic compatibility.
SOLUTION: The substrate for package is provided with: a core substrate 1 which is made of conductive metal and is provided with holes 1A into which coaxial cables 2 covered with a shield coating 2A can be inserted; the coaxial cables 2 whose ends are inserted into the holes 1A, and whose shield coating 2A is electrically connected to the peripheral borders of the holes 1A; an insulating resin 3 which fills the two faces of the core substrate 1 into which the ends of the coaxial cables 2 are inserted, and which has a surface exhibiting the same plane as the ends of the coaxial cables 2; and electrode pads 4 which are formed on the edges of center conductors 3B at the ends of the coaxial cables 2 which appear on the same plane as the insulating resin 3.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了提供几乎不受寄生电感或寄生电容的影响的高频半导体封装的衬底，因此显示出小的传输损耗，并且表现出高度的电磁兼容性。解决方案：用于封装的基板设置有：由导电金属制成的芯基板1，并且设置有孔1A，可以插入用屏蔽涂层2A覆盖的同轴电缆2; 其端部插入孔1A中并且其屏蔽涂层2A电连接到孔1A的周边边缘的同轴电缆2; 绝缘树脂3，其填充芯基板1的两个同轴电缆2的端部插入其中并且具有与同轴电缆2的端部相同的平面的表面; 以及形成在与绝缘树脂3在同一平面上的同轴电缆2的端部处的中心导体3B的边缘上的电极焊盘4.（C）2006，JPO＆NCIPI

10. 发明专利

JP2004289114A Packaging substrate and its manufacturing method 审中-公开
标题翻译：包装基板及其制造方法
公开(公告)号：JP2004289114A
公开(公告)日：2004-10-14
申请号：JP2003359249
申请日：2003-10-20
申请人： Fujitsu Ltd , 富士通株式会社
发明人： MIZUTANI DAISUKE , YONEDA YASUHIRO , MOTOYOSHI KATSUSADA
IPC分类号： H05K1/11 , H05K1/03 , H05K3/00
摘要： PROBLEM TO BE SOLVED: To provide a packaging substrate such as a package substrate with low thermal expansion permitting microfabrication and suited for packaging an electron device at a low cost, concerning the packaging substrate and its manufacturing method.
SOLUTION: There is provided a conductor circuit pattern 8 on at least one surface of a carbon fiber resin board 4 that is formed by laminating prepregs 1 with carbon fibers 2 arranged in one direction in such a manner that the directions in which the carbon fibers 2 are oriented differ.
COPYRIGHT: (C)2005,JPO&NCIPI

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