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1. 发明专利

JP2007243106A Semiconductor package structure 审中-公开
标题翻译：半导体封装结构
公开(公告)号：JP2007243106A
公开(公告)日：2007-09-20
申请号：JP2006067289
申请日：2006-03-13
申请人： Fujitsu Ltd , 富士通株式会社
发明人： SATO TOSHINAO , YOSHIMURA HIDEAKI , FUKUSONO KENJI , KOIDE MASATERU
IPC分类号： H01L23/40
CPC分类号： H01L2224/16225 , H01L2224/26175 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2924/15311 , H01L2924/19105 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To surely prevent failure generation in the case of the soldering operation of a heat spreader concerning a semiconductor package structure. SOLUTION: The semiconductor package structure is provided with a semiconductor chip 2 mounted on a package substrate 1 and a heat spreader 3 soldered to an opposite face to the circuit face of the semiconductor 2. A frame-shaped solder dam 4 surrounding a region including the semiconductor chip 2 from a plane view is formed on a junction surface between the heat spreader 3 and the semiconductor chip 2. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了可靠地防止在关于半导体封装结构的散热器的焊接操作的情况下产生故障。解决方案：半导体封装结构设置有安装在封装基板1上的半导体芯片2和焊接到与半导体2的电路面相反的面的散热器3。在散热器3和半导体芯片2之间的接合表面上形成从平面视图包括半导体芯片2的区域。（C）2007，JPO＆INPIT

2. 发明专利

JP2010129942A Circuit board and its production process, as well as semiconductor device and its production process 审中-公开
标题翻译：电路板及其生产工艺，作为半导体器件及其生产工艺
公开(公告)号：JP2010129942A
公开(公告)日：2010-06-10
申请号：JP2008305982
申请日：2008-12-01
申请人： Fujitsu Ltd , 富士通株式会社
发明人： KURASHINA MAMORU , MIZUTANI DAISUKE , KOIDE MASATERU
IPC分类号： H05K3/46 , H01L23/12 , H01L23/14
CPC分类号： H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/15311 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a circuit board and its production process, as well as a semiconductor device and its production process, by which reliability is improved.
SOLUTION: There is provided a laminate body 10 including a plurality of wiring layers 24, 32, 40, 48, 56 and a plurality of insulating layers 18H, 26H, 34L, 42L, 50H, 58H which are layered alternately. The elasticity modulus of the insulating layers 50H, 58H in a first portion 12 on one side of the laminate body and the elasticity modulus of the insulating layers 18H, 26H in a second portion 14 on the other side of the laminate body are higher than that of the insulating layers 34L, 42L in a third portion 16 interposed between the first and second portions.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供电路板及其制造方法，以及提高可靠性的半导体器件及其制造工艺。解决方案：提供层叠体10，其包括多个交替层叠的多个布线层24,32,40,48,56以及多个绝缘层18H，26H，34L，42L，50H，58H。层压体一侧的第一部分12中的绝缘层50H，58H的弹性模量和层压体另一侧的第二部分14中绝缘层18H，26H的弹性模量高于在插入在第一和第二部分之间的第三部分16中的绝缘层34L，42L。版权所有（C）2010，JPO＆INPIT

3. 发明专利

JP2004342762A Circuit board 审中-公开
公开(公告)号：JP2004342762A
公开(公告)日：2004-12-02
申请号：JP2003136268
申请日：2003-05-14
申请人： Fujitsu Ltd , 富士通株式会社
发明人： UMEMATSU MIMIO , KOIDE MASATERU , OSAWA TAKUMI
IPC分类号： H05K1/02 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To make it a subject that generation of a short circuit between wiring layers formed on both sides of an insulator layer is prevented, when contamination invades into the insulator layer, relating to a circuit board wherein the wiring layer is so formed that the upper and the lower sides are inserted through the insulator layer.
SOLUTION: In the circuit board of construction wherein a power supply solid pattern 13A and a grand solid pattern 14A are laminated on the insulator layer 12, constitution is used that a formation position of the power supply solid pattern 13A (power supply side extrusion part 20a) and a forming position of the ground solid pattern 14A (ground side extrusion part 21A) are deviated from each other, in such a manner that the power supply solid pattern 13A (power supply side extrusion part 20A) and the ground solid pattern 14A (ground side extrusion part 21A) do not overlap in the lamination direction (Z direction).
COPYRIGHT: (C)2005,JPO&NCIPI

4. 发明专利

JP2014007207A Mounting structure for semiconductor device 有权
标题翻译：半导体器件的安装结构
公开(公告)号：JP2014007207A
公开(公告)日：2014-01-16
申请号：JP2012140257
申请日：2012-06-21
申请人： Fujitsu Ltd , 富士通株式会社
发明人： WATANABE MANABU , KOIDE MASATERU , FUKUSONO KENJI , SUGATA TAKASHI
IPC分类号： H05K1/14 , H01L25/00
CPC分类号： H01L21/50 , H01L21/82 , H01L29/06 , H01L2924/15311 , H01L2924/19106 , H05K1/141 , H05K3/323 , H05K3/368 , H05K2201/2018
摘要： PROBLEM TO BE SOLVED: To resolve a problem in which further increase in density and performance of a semiconductor device to be mounted on an information device may cause that even an inductance component of a plating through hole penetrating through a core layer of a build-up substrate of the semiconductor device becomes a primary factor in increase of noise, and to provide a highly-reliable mounting structure for a semiconductor device capable of reducing the inductance component by using a coreless substrate instead of the build-up substrate.SOLUTION: A mounting structure for a semiconductor device includes: a mounting substrate provided with an opening; a frame part provided at an edge part of the opening, and housed in the edge part; a frame-like member composed of a protrusion part protruded from the frame part; a coreless substrate arranged on the mounting substrate, and supported by the protrusion part of the frame-like member; and a semiconductor element arranged on the coreless substrate.
摘要翻译：要解决的问题：为了解决要安装在信息装置上的半导体装置的密度和性能的进一步增加的问题可能导致即使电穿孔的电感分量穿过积层的核心层半导体器件的衬底成为增加噪声的主要因素，并且通过使用无芯衬底代替堆积衬底，能够提供可降低电感成分的半导体器件的高度可靠的安装结构。解决方案：安装半导体器件的结构包括：设置有开口的安装基板; 框架部分，设置在开口的边缘部分，并容纳在边缘部分中; 框架状构件，其由从框架部突出的突出部构成; 无芯基板，其布置在所述安装基板上，并且由所述框架构件的突出部支撑; 以及设置在无芯基板上的半导体元件。

5. 发明专利

JP2011142157A Electronic apparatus and method of manufacturing the same 有权
标题翻译：电子装置及其制造方法
公开(公告)号：JP2011142157A
公开(公告)日：2011-07-21
申请号：JP2010001114
申请日：2010-01-06
申请人： Fujitsu Ltd , 富士通株式会社
发明人： KURASHINA MAMORU , MIZUTANI DAISUKE , FUKUMORI HIROMASA , KOIDE MASATERU , FUKUSONO KENJI
IPC分类号： H01L23/12 , H01L23/36 , H01L23/473
CPC分类号： H01L2224/16225 , H01L2224/73253 , H01L2224/92225 , H01L2924/15311
摘要： PROBLEM TO BE SOLVED: To suppress the deterioration of the reliability of an electronic apparatus caused by thermal stress. SOLUTION: A lid 14 is positioned via a joint member 17 on a semiconductor chip 13 mounted to a package base 11. The package base 11 and the lid 14 have respective holes 11a, 14a, and rivet-shaped pins 15 are inserted into the holes 11a, 14a to fix the package base and the lid in place. Shafts 15a of the pins 15 are inserted into the holes 11a, 14a and heads 15b are locked to the package base 11, whereby the package base 11 is secured to the lid 14 by the pins 15. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：抑制由热应力引起的电子设备的可靠性的劣化。解决方案：盖子14通过连接件17定位在安装到包装基座11上的半导体芯片13上。封装基座11和盖子14具有各自的孔11a，14a，铆钉形销15插入进入孔11a，14a，将包装基座和盖子固定就位。销15的轴15a插入到孔11a，14a中，并且头15b被锁定到包装基座11上，由此通过销15将包装基座11固定到盖14上。版权所有（C）2011 ，JPO＆INPIT

6. 发明专利

JP2011082222A Interconnect board, printed circuit board unit, and method of manufacturing interconnect board 有权
标题翻译：互连板，印刷电路板单元及制造互连板的方法
公开(公告)号：JP2011082222A
公开(公告)日：2011-04-21
申请号：JP2009230913
申请日：2009-10-02
申请人： Fujitsu Ltd , 富士通株式会社
发明人： KOIDE MASATERU
IPC分类号： H01L23/32 , H05K1/14 , H05K3/06 , H05K3/20
CPC分类号： H05K3/4608 , H01L23/13 , H01L23/49816 , H01L23/49827 , H01L23/49833 , H01L24/16 , H01L2224/16 , H01L2924/01078 , H01L2924/01087 , H01L2924/12042 , H01L2924/15311 , H01L2924/19106 , H05K1/141 , H05K3/445 , H05K2201/10378 , H05K2201/10477 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To mount a semiconductor element package on a circuit board without increasing a cost while reducing noise and stabilizing electrical characteristics of the semiconductor element package and the circuit board. SOLUTION: An interconnect board 20 includes: a first insulating layer 21-1; a first metal plate 22-1 involved in the first insulating layer 21-1; a second insulating layer 21-2; a second metal plate 22-2 involved in the second insulating layer 21-2; an insulating base material 28 between laminated layers of the first insulating layer 21-1 and the second insulating layer 21-2; and a metal pile 24 penetrating through the first insulating layer 21-1, the first metal plate 22-1, the insulating base material 28, the second metal plate 22-2, and the second insulating layer 21-2 from a surface mounting a first circuit board 10 to a surface facing a second circuit board 30. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：将半导体元件封装安装在电路板上而不增加成本，同时降低半导体元件封装和电路板的噪声和稳定电特性。解决方案：互连板20包括：第一绝缘层21-1; 涉及第一绝缘层21-1的第一金属板22-1; 第二绝缘层21-2; 涉及第二绝缘层21-2的第二金属板22-2; 在第一绝缘层21-1和第二绝缘层21-2的层压层之间的绝缘基材28; 以及从安装了第一绝缘层21-1，第一金属板22-1，绝缘基材28，第二金属板22-2和第二绝缘层21-2的第一绝缘层21-1，第一电路板10到面向第二电路板30的表面。版权所有（C）2011，JPO＆INPIT

7. 发明专利

JP2011044557A Method of manufacturing multi-chip module, and multi-chip module 有权
标题翻译：制造多芯片模块的方法和多芯片模块
公开(公告)号：JP2011044557A
公开(公告)日：2011-03-03
申请号：JP2009191271
申请日：2009-08-20
申请人： Fujitsu Ltd , 富士通株式会社
发明人： KOIDE MASATERU , MIZUTANI DAISUKE
IPC分类号： H01L25/04 , H01L25/18
CPC分类号： H01L24/17 , H01L23/13 , H01L23/49822 , H01L23/49827 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0655 , H01L25/50 , H01L2224/05647 , H01L2224/13099 , H01L2224/48137 , H01L2224/49175 , H01L2224/73207 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01083 , H01L2924/014 , H01L2924/10253 , H01L2924/15311 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： PROBLEM TO BE SOLVED: To precisely connect LSI chips to each other by bonding wires.
SOLUTION: A plurality of LSI chips 30A to 30D are fixed to a surface of one side of a flat plate type heat spreader 50 through solder bumps 40, the LSI chips are connected by bonding wires 27 on surfaces of the plurality of LSI chips on opposite sides from the heat spreader, and a package substrate 10 is electrically connected on the surfaces of the LSI chips on the opposite side from the heat spreader. Consequently, wire bonding is carried out in a state where the LSI chips are already fixed to the heat spreader, i.e. a state where lower surfaces of the LSI chips are substantially equalized in height.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：通过接合线将LSI芯片彼此精确连接。解决方案：多个LSI芯片30A至30D通过焊料凸块40固定在平板式散热器50的一侧的表面上，LSI芯片通过在多个LSI的表面上的接合线27连接在散热器的相对侧的芯片上，封装基板10与散热器相反一侧的LSI芯片的表面电连接。因此，在LSI芯片已经固定到散热器的状态下，即LSI芯片的下表面的高度大致相等的状态下进行引线接合。版权所有（C）2011，JPO＆INPIT

8. 发明专利

JP2010129810A Semiconductor device mounting board and semiconductor device 有权
标题翻译：半导体器件安装板和半导体器件
公开(公告)号：JP2010129810A
公开(公告)日：2010-06-10
申请号：JP2008303577
申请日：2008-11-28
申请人： Fujitsu Ltd , 富士通株式会社
发明人： KURASHINA MAMORU , MIZUTANI DAISUKE , KOIDE MASATERU
IPC分类号： H01L23/12
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device mounting board that achieves improvement in reliability, and to provide a semiconductor device.
SOLUTION: The semiconductor device mounting board includes: a circuit board 10 having a plurality of electrodes 12 formed on one surface; and a plate 16 which is provided on one surface side of the circuit board, has a plurality of through-holes 20 formed corresponding to the plurality of electrodes 12, and is made of a material having a smaller coefficient of thermal expansion than the circuit board.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种实现可靠性提高的半导体器件安装板，并提供半导体器件。解决方案：半导体器件安装板包括：电路板10，其具有形成在一个表面上的多个电极12; 并且设置在电路板的一个表面侧上的板16具有对应于多个电极12形成的多个通孔20，并且由具有比电路板的热膨胀系数小的材料制成。版权所有（C）2010，JPO＆INPIT

9. 发明专利

JP2006080349A Substrate manufacturing method, and circuit board 有权
标题翻译：基板制造方法和电路板
公开(公告)号：JP2006080349A
公开(公告)日：2006-03-23
申请号：JP2004263729
申请日：2004-09-10
申请人： Fujitsu Ltd , 富士通株式会社
发明人： KOIDE MASATERU
IPC分类号： H05K3/46
CPC分类号： H01L23/50 , H01L23/13 , H01L23/49816 , H01L23/49827 , H01L2224/16235 , H01L2224/16237 , H01L2924/01025 , H01L2924/01078 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/19106 , H05K1/183 , H05K3/0035 , H05K3/0044 , H05K3/381 , H05K3/4644 , H05K3/4697 , H05K2201/09127 , H05K2201/09472 , H05K2201/10636 , H05K2203/0228 , Y02P70/611
摘要： PROBLEM TO BE SOLVED: To create conductor patterns in the inside of a substrate and expose to the external some portions of the conductor patterns at a low cost in a short time without roughing their surfaces, with respect to a substrate manufacturing method etc. which has a laminating process for obtaining the substrate of a multilayer structure, wherein insulating layers and the conductor patterns are laminated alternately and has a processing process for processing the substrate obtained by the execution of the laminating process. SOLUTION: In the laminating process, there is included a second step wherein a second insulating layer 30 is so laminated on conductor patterns 20 formed finally in a first step as to rough a surface 30a of the laminated second insulating layer 30 except for a desired region S and as to form thereafter conductor layers 21 in at least the region S of the surface 30a of the second insulating layer 30. Further, the processing process has a removing step for removing portions R present above the region S which are also present in the higher layers than the second insulating layer 30 of a substrate 1, and has an exposing step for exposing to the external portions 25 of the adjacent conductor patterns 20 to each other which are present in the region S and are present under the second insulating layer 30. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了在基板内部形成导体图案，并且在短时间内以低成本暴露于导体图案的外部部分，而不会使其表面粗糙，相对于基板制造方法等其具有用于获得多层结构的基板的层压工艺，其中绝缘层和导体图案交替层叠，并且具有用于处理通过执行层压处理获得的基板的处理过程。解决方案：在层压过程中，包括第二步骤，其中第二绝缘层30被层压在最终形成在第一步骤中的导体图案20上，以使得层压的第二绝缘层30的表面30a粗糙期望的区域S，并且至少在第二绝缘层30的表面30a的区域S中形成导体层21.此外，处理工艺具有去除存在于区域S之上的部分R的去除步骤，存在于比衬底1的第二绝缘层30更高的层中，并且具有暴露步骤，用于暴露于存在于区域S中并存在于第二区域中的相邻导体图案20的彼此的外部部分25 绝缘层30.版权所有（C）2006，JPO＆NCIPI

10. 发明专利

JP2014192416A Wiring board and electronic device 有权
标题翻译：接线板和电子设备
公开(公告)号：JP2014192416A
公开(公告)日：2014-10-06
申请号：JP2013067954
申请日：2013-03-28
申请人： Fujitsu Ltd , 富士通株式会社
发明人： MIZUTANI DAISUKE , KAWAI KENICHI , TAKEMOTO TAKAHITO , KOIDE MASATERU
IPC分类号： H01L23/12 , H05K1/02 , H05K3/46
CPC分类号： H05K1/0216 , H01L2224/16 , H01L2924/15174 , H01L2924/15311 , H05K1/0222 , H05K1/0228 , H05K1/0231 , H05K1/0251 , H05K1/115 , H05K2201/10734
摘要： PROBLEM TO BE SOLVED: To suppress crosstalk at a junction between a wiring board and a component.SOLUTION: A wiring board 10 includes: ground electrodes 21 arranged at respective apexes of a rectangular region 20A on a surface 11 of the wiring board 10; and a pair of signal electrodes 22 which is arranged in the rectangular region 20A on the surface 11 and is provided in parallel in a direction S in parallel with one side 23 of the rectangular region 20A. Thereby, a junction between the signal electrode 22 of the wiring board 10 and a signal electrode of a component are surrounded by junctions between the ground electrodes 21 of the wiring board 10 and ground electrodes of the component, which suppresses crosstalk at the junction of the signal electrode 22.
摘要翻译：要解决的问题：为了抑制布线基板和部件之间的连接处的串扰。解决方案：布线板10包括布置在布线板10的表面11上的矩形区域20A的各顶点处的接地电极21; 以及一对信号电极22，其布置在表面11上的矩形区域20A中，并且在与矩形区域20A的一个侧面23平行的方向S上平行设置。由此，布线基板10的信号电极22与部件的信号电极之间的接合部被布线基板10的接地电极21与部件的接地电极之间的接点包围，该接地电极抑制了部件的接合处的串扰信号电极22。

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