专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JPS5948891A Electronic circuit device of semiconductor circuit configuration 失效
标题翻译：半导体电路配置的电子电路设备
公开(公告)号：JPS5948891A
公开(公告)日：1984-03-21
申请号：JP15865582
申请日：1982-09-10
申请人： Fujitsu Ltd
发明人： AOYAMA KEIZOU , AZUMA KENJI , SUZUKI YASUAKI
IPC分类号： G11C11/41 , G11C11/34 , G11C11/407
CPC分类号： G11C11/34
摘要： PURPOSE:To supply the electric power only in a desired period, by providing a power supply control unit for each block of semiconductor circuits which are successively actuated. CONSTITUTION:Power supply control units 3-1-3-5 are provided to semiconductor blocks 2-1-2-5 respectively including an address buffer, a decoder, a memory cell, a sense amplifier, an output buffer, etc. of an electronic circuit device such as an electronic memory circuit device 1, etc. These units 3-1-3-4, etc. are controlled by the detection output of input variations obtained by an input variation detecting circuit 4. Then the electric power is supplied to the blocks 2-1-2-4 only in a desired period. This can reduce the power consumption of an electronic circuit device of semiconductor configuration.
摘要翻译：目的：仅在期望的时间内提供电力，通过为连续致动的每个半导体电路块提供电源控制单元。构成：电源控制单元3-1-3-5被提供给分别包括地址缓冲器，解码器，存储单元，读出放大器，输出缓冲器等的半导体块2-1-2-5 诸如电子存储器电路器件1的电子电路器件等。这些单元3-1-3-4等由输入变化检测电路4获得的输入变化的检测输出控制。然后提供电力仅在期望的时间段内到块2-1-2-4。这可以降低半导体配置的电子电路器件的功耗。

2. 发明专利

JPS5690483A ADDRESS BUFFER CIRCUIT 失效
公开(公告)号：JPS5690483A
公开(公告)日：1981-07-22
申请号：JP16523279
申请日：1979-12-19
申请人： FUJITSU LTD
发明人： ITOU HIDEAKI , AZUMA KENJI
IPC分类号： G11C11/41 , G11C8/00 , G11C11/413 , G11C11/418
摘要： PURPOSE:To prevent flowing of wasteful current by adding a simple modification to an address buffer circuit of latch type in a CMIS-RAM. CONSTITUTION:Usually, latch signals phi, phi' are generated by input clock, and the input address in the predetermined period before and after these is latched as effective. In addition to this, a latch signal phi* is generated by a clock circuit 5 and is applied to transistors TR4 and 6. As a result, during the latching, the TR4 is on and the TR6 is off, and ordinary latching operation takes place. When the latch signal phi* annihilates, the TR4 goes off and the TR6 goes on; therefore, no matter how the input address changes, the current does not flow to the transistors 1 and 2 constituting an inverter.

3. 发明专利

JPS6375889A MEMORY CARD 失效
公开(公告)号：JPS6375889A
公开(公告)日：1988-04-06
申请号：JP21817286
申请日：1986-09-18
申请人： FUJITSU LTD
发明人： AZUMA KENJI
IPC分类号： G06K19/07 , B42D15/02 , B42D15/10 , G06K19/00
摘要： PURPOSE:To surely prevent the entering of static electricity or noise signals, etc. into a memory card from the external even when they are impressed by executing the cutting-off by means of duplex switch elements. CONSTITUTION:At the standby of a memory, by turning the voltage of a control signal impressed to a control signal terminal B to a low level, the control voltage supplied to the switch elements A12, An2 can be quickly lowered to the low level by means of a resistor R4, thus the switch elements A12, An2 are turned OFF, to cut off input signals I1, In. Moreover, when the memory card is extracted or the external power source is cut off, the control voltage supplied to the switch elements A11, An1 is quickly lowered to a low level by a resistor R3 to turn OFF the elements A11, An1. In such a time, the switch elements A12, An2 are also turned OFF. Thus, the connection between the card I/O terminals I1, In and the I/O terminals I1', In' of the memory are cut off in double manners.

4. 发明专利

JPH0514313B2 失效
公开(公告)号：JPH0514313B2
公开(公告)日：1993-02-24
申请号：JP21817286
申请日：1986-09-18
申请人： FUJITSU LTD
发明人： AZUMA KENJI
IPC分类号： G06K19/07 , B42D15/02 , B42D15/10 , G06K19/00

5. 发明专利

JPS5522238A DECODER CIRCUIT 失效
公开(公告)号：JPS5522238A
公开(公告)日：1980-02-16
申请号：JP9350278
申请日：1978-07-31
申请人： FUJITSU LTD
发明人： ITOU HIDEAKI , AZUMA KENJI , NOGUCHI EIJI
IPC分类号： G11C11/41 , G11C11/413 , G11C11/418 , G11C11/419 , H03M7/00
摘要： PURPOSE:To omit the gate for the clock and its wiring by including the clock information into one of the address signals, thus simplifying the constitution of the decoder circuit as well as reducing the occupied area. CONSTITUTION:Address signal A4* containing the clock information is produced from address signal 4A through the circuit comprising MOSFETQ11-Q16. Single conduction channel type MOSFETQ1 to which signal A4* is applied and FETQ1 to which signal A4* plus other address signal are applied are connected in series to opposite conduction channel type MOSFETQ2-Q6. The outpur is then drawn out at the joints of the above FET's via output line l in order to decrease one gate for the clock. The circuit to produce the address signal containing the clock information is required, but the constitution can be simplified greatly as a whole since the number of the gate is multiplied as much as the number of the column.

6. 发明专利

JPH0547874B2 失效
公开(公告)号：JPH0547874B2
公开(公告)日：1993-07-19
申请号：JP21732086
申请日：1986-09-17
申请人： FUJITSU LTD
发明人： AZUMA KENJI
IPC分类号： G06K19/07 , G06K19/00 , G06K19/073 , G11C7/00

7. 发明专利

JPS6322387B2 失效
公开(公告)号：JPS6322387B2
公开(公告)日：1988-05-11
申请号：JP17428782
申请日：1982-10-04
申请人： FUJITSU LTD
发明人： AOYAMA KEIZO , AZUMA KENJI , SUZUKI YASUAKI
IPC分类号： G11C11/41 , G11C8/00 , G11C8/18 , H03K19/003

8. 发明专利

JPS6373389A MEMORY CARD 失效
公开(公告)号：JPS6373389A
公开(公告)日：1988-04-02
申请号：JP21732086
申请日：1986-09-17
申请人： FUJITSU LTD
发明人： AZUMA KENJI
IPC分类号： G06K19/07 , G06K19/00 , G06K19/073 , G11C7/00
摘要： PURPOSE:To prevent the destructing of memory data by making forcibly a memory loaded to a card into a non-writing condition when an external source voltage is not impressed to an external power terminal. CONSTITUTION:A memory card has an external power terminal S, a terminal I1 (writing enable signal WE) and a terminal In (chip selecting signal CS). When the card is pulled out from the external power source or the power source is turned off, the potential of an A point comes to be a low level. Consequently, regardless of the level of respective signals inputted from terminals I1.In, the signal level inputted to terminals I'1 and I'n comes to be forcibly the high level and a memory M is made into a standby condition. For such a reason, even when the static electricity or noise signal of the high level is mixed from the terminals I1 and In, memory data are held without fail and the destruction of the data is prevented.

9. 发明专利

JPS5963094A Memory device 失效
标题翻译：内存设备
公开(公告)号：JPS5963094A
公开(公告)日：1984-04-10
申请号：JP17428782
申请日：1982-10-04
申请人： Fujitsu Ltd
发明人： AOYAMA KEIZOU , AZUMA KENJI , SUZUKI YASUAKI
IPC分类号： G11C11/41 , G11C8/00 , G11C8/18 , H03K19/003 , G11C11/34
CPC分类号： H03K19/00361 , G11C8/00 , G11C8/18
摘要： PURPOSE: To prevent the increment of the power consumption, by providing an address change detecting circuit and invalidating a power supply circuit for an address decoding circuit for a predetermined period by the output of this detecting circuit.
CONSTITUTION: Respective bits A
0 , A
1 WA
m of address information are supplied to an address change detecting circuit 4; and when any bit is changed, the circuit 4 generates control signals ϕ and -ϕ for a prescribed time. Control signals -ϕ and ϕ are supplied to transistors 5 and 6, and an output X is invalidated while control signals ϕ and -ϕ exist. If the power-down state is set apparently, only a decoding circuit to detect the address change correctly is operated.
COPYRIGHT: (C)1984,JPO&Japio
摘要翻译：目的：为了防止功耗的增加，通过提供地址变化检测电路，并且通过该检测电路的输出使地址解码电路的电源电路达到预定周期。构成：将地址信息的相应位A0，A1-Am提供给地址变化检测电路4; 并且当任何位被改变时，电路4在规定的时间内产生控制信号phi和-phi。控制信号-phi和phi被提供给晶体管5和6，并且输出X无效，同时存在控制信号phi和-phi。如果掉电状态设置明显，则仅操作用于检测地址改变的解码电路。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式