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1. 发明专利

JPH11243332A CMOS GATE CIRCUIT 失效
公开(公告)号：JPH11243332A
公开(公告)日：1999-09-07
申请号：JP14584698
申请日：1998-05-27
申请人： FUJITSU LTD
发明人： SUZUKI YASUAKI , SHIINE MASARU , HORIE MASAYUKI , SUWA SUSUMU
IPC分类号： H03K17/16 , H03K17/687 , H03K19/0175 , H03K19/0948
摘要： PROBLEM TO BE SOLVED: To provide a CMOS gate circuit which reduces output distortions due to capacitive load, also has small power consumption while suppressing an internal through current and is also manufactured inexpensively without changing a conventional manufacturing process. SOLUTION: A 2nd P-channel type MOS transistor 7 and a 2nd N-channel type MOS transistor 8 are added to a gate where the drains of a 1st P-channel type MOS transistor 2 and a 1st N-channel MOS type transistor 3 are connected to each other and both the transistors 7 and 8 are turned on for a prescribed time only at the time of the rise and fall of output signal. Also, a delay gate and a through current inhibit gate are added to the transistors 2 and 3 and the through current is prevented by shifting an off state during delay time 'of the delay gate when both the transistors 2 and 3 alternate on and off.

2. 发明专利

JPH0451918B2 失效
公开(公告)号：JPH0451918B2
公开(公告)日：1992-08-20
申请号：JP18201283
申请日：1983-09-30
申请人： FUJITSU LTD
发明人： SUZUKI YASUO , HIRAO HIROSHI , SUZUKI YASUAKI
IPC分类号： G11C17/18 , G11C11/417 , G11C11/56 , G11C16/04 , H01L27/10

3. 发明专利

JPH01294300A METHOD FOR IDENTIFYING MASK ROM WRITE DATA 失效
公开(公告)号：JPH01294300A
公开(公告)日：1989-11-28
申请号：JP12545388
申请日：1988-05-23
申请人： FUJITSU LTD
发明人： SUZUKI YASUAKI
IPC分类号： G11C29/00 , G11C16/02 , G11C17/00 , G11C29/12
摘要： PURPOSE:To eliminate a need of the stage of a special wafer process before as well as after packaging and to easily and surely identify write data by applying a voltage higher than the normal operating voltage to an input signal line to detect whether the input signal line is made conductive or not. CONSTITUTION:Plural MOS transistors TRs 11 are connected in series between a MOS TR 10 for data write due to ion implantation and an input signal line 12 for the purpose of obtaining the sum of threshold voltages higher than the normal operating voltage of the MOS TR. At the time of identifying write data, the voltage higher than the normal operating voltage is applied to the input signal line 12 to detect whether the input signal line 12 is made conductive or not, thereby identifying write data of the MOS TR 10 for data write. Thus, the stage of a special wafer process is unnecessary before as well as after packaging, and write data is easily and surely identified.

4. 发明专利

JPS633451A MANUFACTURE OF MASK ROM 失效
公开(公告)号：JPS633451A
公开(公告)日：1988-01-08
申请号：JP14618886
申请日：1986-06-24
申请人： FUJITSU LTD
发明人： SUZUKI YASUAKI , MIZOBE KENJI
IPC分类号： H01L21/8246 , H01L27/112
摘要： PURPOSE:To implement a high speed by decreasing the resistance value of word lines and to shorten a turnaround time, by forming the gate electrode of a cell transistor with double layers, removing a part of the upper layer, and implanting ions. CONSTITUTION:On a semiconductor substrate 1, a field oxide film 2 as an isolating and insulating layer and a gate oxide film 3 of a cell transistor are formed. A gate electrode comprising double layers, i.e., word lines WLs, is formed. The word lines WLs are constituted by a polysilicon layer 4-1 and a silicide layer 4-2. When writing is performed in the cell transistor, the layer 4-2 on the gate of the cell transistor is selectively etched away. B ions and the like are implanted in a part, where the layer 4-2 is removed, and the threshold voltage value of the cell transistor is changed. Thus the writing of the data is performed.

5. 发明专利

JPS6061997A MEMORY EXCLUSIVE FOR MULTI-LEVEL READING 失效
公开(公告)号：JPS6061997A
公开(公告)日：1985-04-09
申请号：JP17079483
申请日：1983-09-16
申请人： FUJITSU LTD
发明人： SUZUKI YASUO , HIRAO HIROSHI , SUZUKI YASUAKI
IPC分类号： G11C16/04 , G11C11/56 , G11C29/00 , H01L27/10
摘要： PURPOSE:To read accurately the storage data of a multi-value memory even in case the resistance of a ground line is not negligible, by producing the reference voltage of an accurate level after compensating a voltage drop. CONSTITUTION:When a memory cell MC is selected by a column address CA and a row address RA, a current flows in a route of a power supply V, a bit line BL, a cell MC and a ground line 10. Then the output of a load circuit 32 is compared with a reference voltages S1-S3 by sense amplifiers 34-38. A cell group 44 for generation of reference voltage consists of the same transistor Q as a memory cell group. A current flows from the power supply V through the transistor Q selected by a column decoder 46 and the line 10, and a load circuit 50 produces an output S1. The voltage drop produced at the position of the selected transistor is equal to the variation of the read output voltage produced at the position of a cell of a memory cell group. Then the output S1 is set at the reference voltage to correct the difference of voltage drop due to positions. This ensures the reading with no error.

6. 发明专利

JPH04357712A CMOS OUTPUT BUFFER CIRCUIT 失效
公开(公告)号：JPH04357712A
公开(公告)日：1992-12-10
申请号：JP13252591
申请日：1991-06-04
申请人： FUJITSU LTD
发明人： SUZUKI YASUAKI
IPC分类号： H01L21/8238 , H01L27/092 , H03K17/16 , H03K17/687 , H03K19/0175
摘要： PURPOSE:To realize a CMOS output buffer circuit in which a through-current is suppressed and the production of spike noise is reduced. CONSTITUTION:The output buffer circuit consists of a P-MOS transistor(TR) Q1 and an N-MOS TR Q2 whose gates are connected respectively to an input terminal A and whose drains are connected together, a P-MOS TR Q3 and an N-MOS TR Q4 whose drains are connected together, and inverters B1, B2 whose input connects to an input terminal A and whose output connects to gates of the P-MOS TR Q3 and N-MOS TR Q4, and sources of the two P-MOS TRs Q1, Q3 connect to a power supply VDD, the two N-MOS TRs Q2, Q4 connect to ground GND, and the drains of the four TRs are connected together and the connecting point is used for an output terminal O.

7. 发明专利

JPH01295516A MALFUNCTION PREVENTING CIRCUIT 失效
公开(公告)号：JPH01295516A
公开(公告)日：1989-11-29
申请号：JP12545288
申请日：1988-05-23
申请人： FUJITSU LTD
发明人： SUZUKI YASUAKI
IPC分类号： H03K5/1252 , H03K5/01
摘要： PURPOSE:To eliminate noise without causing the reduction in fan-out, reduction in the mount density and any cost-up by providing a delay circuit outputting plural delay signals and a logic circuit taking majority decision logic of plural delay signals and giving an output. CONSTITUTION:A delay circuit 10 gives delays of '0', t and t2 to a digital input signal to generate three delay signals. A logic circuit 12 takes majority decision logic of the three signals. For example, suppose that noise is superimposed on, e.g., a digital signal and the signal level is changed momentarily to a high level, then the high level is given to the logic circuit 12 as it is and delayed by t and t2 the result is given to the logic circuit 12. As a result, when one of inputs to the logic circuit 12 is at a high level, the other two inputs are at a low level without fail. Thus, the majority decision logic results in a low level. The noise is eliminated from the input signal as the output of the logic circuit 12.

8. 发明专利

JPS6141078B2 失效
公开(公告)号：JPS6141078B2
公开(公告)日：1986-09-12
申请号：JP17079483
申请日：1983-09-16
申请人： FUJITSU LTD
发明人： SUZUKI YASUO , HIRAO HIROSHI , SUZUKI YASUAKI
IPC分类号： G11C16/04 , G11C11/56 , G11C29/00 , H01L27/10

9. 发明专利

JPS6010495A SENSE AMPLIFIER 失效
公开(公告)号：JPS6010495A
公开(公告)日：1985-01-19
申请号：JP11861883
申请日：1983-06-30
申请人： FUJITSU LTD
发明人： SUZUKI YASUO , HIRAO HIROSHI , SUZUKI YASUAKI
IPC分类号： G11C7/06 , G11C11/409 , G11C11/419 , G11C11/56 , G11C11/34
摘要： PURPOSE:To furnish a circuit suitable for multi-value level memory that can perform accurate operation even when input power varies remarkably and accordingly reference voltage becomes low by making a power source to a flip flop circuit off until just before starting sense operation. CONSTITUTION:Clocks CLKn, CLKp applied to switching circuits Q5, Q6 and Q11, Q12 are so designed that CLKn rises first and then CLKp falls. At first CLKn is L level, and CLKp is H level and a flip flop circuit FF does not operate. When a memory cell is read out and the output D is applied to a transistor Q7, CLKn rises, and Q6 becomes on and Q5 becomes off. However, as Q12 is in and Q11 is off, the current of passage Vcc, Q3, P1, Q8, ground and Vcc, Q4, P2, Q12, ground does not flow. Then, CLKp falls, Q11 becomes on, Q12 becomes off, and the voltage of a power source Vcc is applied to the flip flop circuit FF. One of transistors Q1, Q2 becomes on, and another becomes off.

10. 发明专利

JPS5948891A Electronic circuit device of semiconductor circuit configuration 失效
标题翻译：半导体电路配置的电子电路设备
公开(公告)号：JPS5948891A
公开(公告)日：1984-03-21
申请号：JP15865582
申请日：1982-09-10
申请人： Fujitsu Ltd
发明人： AOYAMA KEIZOU , AZUMA KENJI , SUZUKI YASUAKI
IPC分类号： G11C11/41 , G11C11/34 , G11C11/407
CPC分类号： G11C11/34
摘要： PURPOSE:To supply the electric power only in a desired period, by providing a power supply control unit for each block of semiconductor circuits which are successively actuated. CONSTITUTION:Power supply control units 3-1-3-5 are provided to semiconductor blocks 2-1-2-5 respectively including an address buffer, a decoder, a memory cell, a sense amplifier, an output buffer, etc. of an electronic circuit device such as an electronic memory circuit device 1, etc. These units 3-1-3-4, etc. are controlled by the detection output of input variations obtained by an input variation detecting circuit 4. Then the electric power is supplied to the blocks 2-1-2-4 only in a desired period. This can reduce the power consumption of an electronic circuit device of semiconductor configuration.
摘要翻译：目的：仅在期望的时间内提供电力，通过为连续致动的每个半导体电路块提供电源控制单元。构成：电源控制单元3-1-3-5被提供给分别包括地址缓冲器，解码器，存储单元，读出放大器，输出缓冲器等的半导体块2-1-2-5 诸如电子存储器电路器件1的电子电路器件等。这些单元3-1-3-4等由输入变化检测电路4获得的输入变化的检测输出控制。然后提供电力仅在期望的时间段内到块2-1-2-4。这可以降低半导体配置的电子电路器件的功耗。

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