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1. 发明专利

JPS57150191A ASYNCHRONOUS TYPE STATIC MOS MEMORY 失效
公开(公告)号：JPS57150191A
公开(公告)日：1982-09-16
申请号：JP3347681
申请日：1981-03-09
申请人： FUJITSU LTD
发明人： ITOU HIDEAKI , SUZUKI ATSUSHI
IPC分类号： G11C11/417 , G11C7/12 , H01L21/8244 , H01L27/11 , H01L29/78
摘要： PURPOSE:To achieve write at a low power consumption and read stably and surely, by reading a current voltage characteristics of a bit line load and changing the result to be suited to write. CONSTITUTION:The gate of P type transistors (TRs) Q11 and Q12 generating a voltage drop proportional to a current the same as a resistor is connected respectively in series with the drain of load TRs Q7 and Q8 of a pair of bit lines Bj0 and Bj1 of a memory cell of an asynchronous type static MOS memory. Thus, when a current flows to the lines Bj0 and Bj1, a current voltage characteristic of the load changed from a curve Ca to a curve Cc, an L level V2 at read is not changed for sure and stable reading, and a current to an L level V3 at reading is decreased from i2 to i4, allowing to achieve the write-in a low power consumption.

2. 发明专利

JPS5787249A MEASURING SYSTEM FOR ERROR RATE 失效
公开(公告)号：JPS5787249A
公开(公告)日：1982-05-31
申请号：JP16312980
申请日：1980-11-19
申请人： FUJITSU LTD
发明人： ITOU HIDEAKI , HODOHARA KIYOAKI
IPC分类号： H04L1/00 , G06F11/34 , H04L1/24
摘要： PURPOSE:To cope with the increment of the number of phases of phase modulation easily, by measuring an error rate in the receiving signal by the number of bits of disaccordant pulses in the simple error rate measuring system using a gray code. CONSTITUTION:A fault location pattern generating circuit 7 which generates an N-digit gray code and transmits it as an N-channel signal is provided in the transmission side, and a fault location pattern detecting circuit 10 which detects the disaccord between respective receiving signals of N channels and signals, which are obtained by delaying these receiving signals by one bit, and counts the number of bits of disaccordant pulses in an output, which is obtained by detecting successively the disaccord in respective detection outputs, is provided in the receiving side. An error rate of the receiving signal is measured by the number of bits of disaccordant pulses. Consequently, this system copes with the increment of the number of phases of phase modulation easily.

3. 发明专利

JPS56149812A ELASTIC SURFACE WAVE DEVICE 失效
公开(公告)号：JPS56149812A
公开(公告)日：1981-11-19
申请号：JP5281980
申请日：1980-04-23
申请人： FUJITSU LTD
发明人： TODA YOSHIFUMI , HODOHARA KIYOAKI , MORITA TOSHIYUKI , ITOU HIDEAKI
IPC分类号： H03H9/25 , H03H3/08 , H03H9/02 , H03H9/05
摘要： PURPOSE:To prevent electric discharge of the element and caused by a pyroelectric effect, by coating the inside surface of a metallic case for enclosing an elastic surface wave element which is used for the filter of VHF and UHF bands, etc., with an insulator. CONSTITUTION:The inside surface of the metallic case 16 is coated with an insulator 17, and an elastic surface wave element 18 is enclosed in said case. As for this insulator 17, epoxy resin, etc. which are excellent in electric insulating property and heat resisting property are used. In this formation, when dielectric strength of the insulator and that of air are denoted as Eb and Ea, respectively, and for instance, they are set as Eb=10Ea, it is possible to prevent electric discharge up to maximum 400 deg.C or so. Also, according to said constitution, electric discharge between the lead wire 19 and the case 16 is also prevented. In this way, generation of a noise due to a pyroelectric effect is prevented.

4. 发明专利

JPS56149110A ELASTIC SURFACE WAVE DEVICE 失效
公开(公告)号：JPS56149110A
公开(公告)日：1981-11-18
申请号：JP5227280
申请日：1980-04-22
申请人： FUJITSU LTD
发明人： TODA YOSHIFUMI , WAKATSUKI NOBORU , MORITA TOSHIYUKI , ITOU HIDEAKI , HODOHARA KIYOAKI
IPC分类号： H03H9/25 , H03H3/08 , H03H9/02 , H03H9/05
摘要： PURPOSE:To earth the surface of an elastic surface wave element electrified by the pyroelectric effect by covering the surface of the elastic surface wave substrate with a high-resistance material before reed screen type electrodes are formed on the surface and then by coating the outer circumference of the substrate top surface and the end surfaces with a conductive material. CONSTITUTION:The top surface of elastic surface wave substrate 18 before reed screen type electrodes 19 of element 17 are formed is coated with a single metal, such as Ta and Mo, or its nitride or oxide, or an alloy material, such as NiCr and NiCr-Si by vacuum vapor deposition or sputtering. Then, the outer circumference of the top surface and end surfaces are coated with conductive material 24, such as Al, by vacuum vapor deposition or sputtering. Consequently, the surface of element 17 electrified by the pyroelectric effect is earthed at bottom plate 16a of metallic case 16 via conductive coating 24, provided on the outer circumference of the top surface of the element and its end surfaces from high-resistance coating 23.

5. 发明专利

JPS56119548A DETECTING CIRCUIT FOR SIGNAL BREAK AND MARK RATE 失效
公开(公告)号：JPS56119548A
公开(公告)日：1981-09-19
申请号：JP2252480
申请日：1980-02-25
申请人： FUJITSU LTD
发明人： TODA YOSHIFUMI , MORITA TOSHIYUKI , ITOU HIDEAKI , HODOHARA KIYOAKI
IPC分类号： H04L1/00 , H04B14/04 , H04L1/20 , H04L25/02
摘要： PURPOSE:To independently determine detection limits of momentary break and the breaking of singal throuh causing the limit of the detection mark rate to aproach 0 or 1, integrating circuit, which has a time constant longer than that of the first integrating circuit connected to the FF, with the reference voltage. CONSTITUTION:When the pulse period of input signal 1 is sufficiently shorter than time constant R1C1 of integrating circuit 14, the level of output signal 4 of integrating circuit 14, the level of output signal 4 of integrating circuit 17 does not reach the threshold and does not generate the alarm signal if input signal 1 is given to clock input terminal C of FF11. When the pulse period of input signal 1 is sufficiently longer than time constant R1C1, the level of output signal 4 increases and exceeds the threshold voltage to generate alarm. When a momentary break sufficiently shorter than time constant C2R2 of integrating circuit 17 is generated in input signal 1, the level of output signal 4 does not reach the threshold and does not generate alarm; but if instantaneous breaking or the breaking of singal sufficiently longer than time constant C2R2 is generated in input signal 1, the level of output signal 4 increases and exceeds the threshold to generate alarm.

6. 发明专利

JPS60173944A ADJACENT CHANNEL IDENTIFICATION SYSTEM 失效
公开(公告)号：JPS60173944A
公开(公告)日：1985-09-07
申请号：JP2900284
申请日：1984-02-17
申请人： FUJITSU LTD
发明人： ITOU HIDEAKI , YANO KOUJI
IPC分类号： H04J1/00 , H04J11/00 , H04J99/00
摘要： PURPOSE:To eliminate the effect of deterioration of the identification capability by replacing properly a signal series. CONSTITUTION:The transmission frequency of system 2 and 3 is identical, the system 2 uses a vertical polarized wave V and the system 3 uses a horizontal polarized wave H, and the connection between demodulators 11, 12 and line switching devices 15, 16 corresponded in a reception section is made opposite to each other. Since a frame synchronism bit is included in a CH1 only, the frame synchronism bit is extracted respectively from terminals 1, 2 of the demodulators 11, 12 to attain frame synchronism normally. If fading takes place, the polarized plane is rotated, the output signal of the system 2 is received by the system 3 and demodulated, then the line switching device 16 cannot synchronize. Thus, entering of a signal of other route is identified and the transmission is stopped.

7. 发明专利

JPS593523A Semiconductor storage device 失效
标题翻译：半导体存储设备
公开(公告)号：JPS593523A
公开(公告)日：1984-01-10
申请号：JP11299682
申请日：1982-06-30
申请人： Fujitsu Ltd
发明人： ITOU HIDEAKI , SUZUKI ATSUSHI
IPC分类号： H02J1/00 , G06F1/26 , G06F1/30 , G11C11/407 , G11C11/413 , H02J9/06
CPC分类号： G06F1/30
摘要： PURPOSE:To keep backup for a memory in case when voltage of a normal use power source drops, without providing a special circuit on the outside, by providing terminals for normal use and emergency use as power supply terminals. CONSTITUTION:A semiconductor storage device MEM is provided with two power supply terminals VS1, VS2, and a normal use power source Vcc1 and an emergency use power source Vcc2 are connected to the terminal VS1 and the terminal VS2, respectively. Also, the storage device MEM contains a detecting circuit DT for detecting a voltage drop of the normal use power source Vcc1. In this state, the power source Vcc1 and Vcc2 are supplied through a diode D1 and D2, and also the whole storage device MEM is set to a stationary state by an output of the detecting circuit DT. In this way, backup for a memory is kept in case of voltage drop of the normal use power source, without providing a special circuit on the outside.
摘要翻译：目的：为了保持正常使用电源电压下降的情况下的内存备份，不需要在外部提供专用电路，通过提供正常使用的终端和紧急用作电源端子。构成：半导体存储装置MEM具有两个电源端子VS1，VS2，正常使用电源Vcc1，紧急用电源Vcc2分别与端子VS1和端子VS2连接。此外，存储装置MEM包含用于检测正常使用电源Vcc1的电压降的检测电路DT。在这种状态下，通过二极管D1和D2提供电源Vcc1和Vcc2，并且通过检测电路DT的输出将整个存储装置MEM设置为静止状态。以这种方式，在正常使用电源的压降的情况下，保持存储器的备份，而不在外部提供专门的电路。

8. 发明专利

JPS57147278A PROTECTING DEVICE FOR MIS INTEGRATED CIRCUIT 失效
公开(公告)号：JPS57147278A
公开(公告)日：1982-09-11
申请号：JP3175181
申请日：1981-03-05
申请人： FUJITSU LTD
发明人： ITOU HIDEAKI , SUZUKI ATSUSHI
IPC分类号： H03F1/52 , H01L27/02 , H01L27/06 , H01L29/78 , H02H7/20 , H03F1/00 , H03F1/42
摘要： PURPOSE:To prevent the adverse influence to a protecting device when negatively excessive noise voltage is applied to an input terminnal by connecting the isolation region of the diffused resistor of the device to a low voltage source via the resistor. CONSTITUTION:A diffused resistor 12 is connected between an input terminal IN and a C-MOS inverter 10, and a diode is connected between the input terminal of the inverter 10 and high and low voltage sources VCC, VSS. Further, a resistor 45 is connected between the isolation region of the resistor 12 and the low voltage source VSS. When the resistor 45 is thus provided, even if negatively excessive noise voltage is applied to the input terminal, the current flowing through the source VSS, resistor 12 and input terminal IN is limited. Accordingly, the burnout due to overcurrent can be prevented.

9. 发明专利

JPS57107652A CODE ERROR RATE MEASURING SYSTEM 失效
公开(公告)号：JPS57107652A
公开(公告)日：1982-07-05
申请号：JP18474180
申请日：1980-12-25
申请人： FUJITSU LTD
发明人： ITOU HIDEAKI , HODOHARA KIYOAKI
IPC分类号： H04L1/00 , H04L1/24
摘要： PURPOSE:To enable the measurement of code error rate at a polyphase modulation of 4-phase or more simply at a state close to a real signal transmission, by spreading a spectrum of radio section, through the use of a PN(pseudo noise) code. CONSTITUTION:A terminal station transmission section G transmits a PN code as a CH1 signal from a PN code generating circuit 20, and the PN code is transmitted as a CH2 signal with one bit delay at a one bit delay circut 21 and as a CH3 signl with two-bit delay at a two-bit delay circuit 23 respectively. At a relay station reception section H, the CH1 signal is delayed by 2-bit at a 2-bit delay circuit 23 and applied to an EXOR circuit 25 with the CH3 signal for exclusive logical sum, and the CH2 signal is delayed by one bit at a one bit delay circuit 24 and applied to an EXOR circuit 26 with the CH3 signal for exclusive logical sum. The both are summed at an OR circuit 27 for error detection output. If there is any error, since (1) pulse appears, the error rate can be known by counting the number of (1) pulses.

10. 发明专利

JPS5797749A SYNCHRONOUS SWITCHING SYSTEM WITHOUT MOMENTARY BREAK 失效
公开(公告)号：JPS5797749A
公开(公告)日：1982-06-17
申请号：JP17439080
申请日：1980-12-10
申请人： FUJITSU LTD
发明人： ITOU HIDEAKI
IPC分类号： H04B1/74 , H04L1/22
摘要： PURPOSE:To switch current and stand-by lines without momentary break, by reading the same data from current and stand-by lines and by adjusting a variable delay means so that phases of them are equal to each other. CONSTITUTION:Data are transmitted in parallel from the transmission terminal toward a current line and a stand-by line. In the current side, data D1 is read by output synchronized with a clock C1, and the signal is outputted through a variable delay circuit 3 and a switching circuit 8. In the stand-by side, the same data D2 is read by the output synchronized with a clock C2, and the signal is outputted through a variable delay circuit 6 and a switching circuit 8. For switching of current and stand-by lines, oscillators 2 and 5 synchronized with respective clocks are controlled to eliminate the phase difference, and the variable delay circuit 6 is so adjusted that the phase difference between output code strings is eliminated. After outputs of current and stand-by lines coincide with each other, they are switched.

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