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1. 发明专利

JP2006134990A Semiconductor apparatus 有权
标题翻译： SEMICONDUCTOR APPARATUS
公开(公告)号：JP2006134990A
公开(公告)日：2006-05-25
申请号：JP2004320322
申请日：2004-11-04
申请人： Fuji Electric Holdings Co Ltd , 富士電機ホールディングス株式会社
发明人： IKEDA YOSHINARI , YAMASHITA MITSUO
IPC分类号： H01L21/52 , H01L25/07 , H01L25/18
CPC分类号： H01L2224/16225 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/49111 , H01L2224/73253 , H01L2924/1305 , H01L2924/13055 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To efficiently dissipate heat from the top face and underside of a package in the package adopting a laminated structure. SOLUTION: A main electrode for a power semiconductor switching element and an electrode for a diode are brought into contact between a first conductor substrate and a second conductor substrate, respectively, and a first parallel connecting circuit is constituted. The main electrode for the power semiconductor switching element and the electrode for the diode are brought into contact between the second conductor substrate and a third conductor substrate, respectively, and a second parallel connecting circuit is constituted. The first parallel connecting circuit and the second parallel connecting circuit are connected in series through the second conductor substrate and sealed with a resin. The power semiconductor switching element and the diode and each conductor substrate are connected at the shrinkage pressure of the sealing resin. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：采用层压结构，在包装的顶面和底面有效散发热量。解决方案：分别在第一导体基板和第二导体基板之间接触用于功率半导体开关元件的主电极和二极管的电极，并且构成第一并联电路。用于功率半导体开关元件的主电极和二极管的电极分别在第二导体基板和第三导体基板之间接触，并且构成第二并联电路。第一并联电路和第二并联电路通过第二导体基板串联连接并用树脂密封。功率半导体开关元件和二极管以及每个导体基板以密封树脂的收缩压力连接。版权所有（C）2006，JPO＆NCIPI

2. 发明专利

JP2006066716A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2006066716A
公开(公告)日：2006-03-09
申请号：JP2004248843
申请日：2004-08-27
申请人： Fuji Electric Holdings Co Ltd , 富士電機ホールディングス株式会社
发明人： IKEDA YOSHINARI , YAMASHITA MITSUO
IPC分类号： H01L23/48 , H01L23/34
CPC分类号： H01L2224/37 , H01L2224/37147 , H01L2224/40 , H01L2224/40095 , H01L2224/40225 , H01L2224/48091 , H01L2224/73265 , H01L2224/77272 , H01L2224/83801 , H01L2224/84801 , H01L2924/13055 , H01L2924/181 , H01L2924/19107 , H01L2924/351 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To improve a fatigue life and reliability of a solder bonding portion by suppressing low the elution of Ni filmed on the surface of a base metal to a solder and the growth of a metal compound generated on a bonding interface with regard to the solder bonding portion between members comprising a module type semiconductor device. SOLUTION: In the module type semiconductor device, a power semiconductor chip 3 is mounted on a conductor pattern 2a of an insulating substrate 2 packaged on a copper base plate 1, and a lead frame 4 is connected to the upper surface electrode of the semiconductor chip. In such a module type semiconductor device soldering respective members and bonding their faces, an Ni film 9 is formed by filming Ni as surface treatment on a solder bonding surface of each of bonding members including the semiconductor chip 3. Further, a Cu film 10 is formed on the surface of the Ni film for thickness (of ≤1 μm) to be perfectly dissolved in solder bonding steps, and the members are then solder-bonded by Sn-rich soldering. Thus, a ternary metal compound of Cu-Ni-Sn is generated on the bonding interface of the solder, this metal compound becomes a barrier to suppress the elution of Ni and the growth of the metal compound with electrification and heating during actual use, thereby improving reliability of the solder bonding portion. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：通过抑制在基体金属表面上焊接到焊料上的Ni的洗脱以及在接合界面上产生的金属化合物的生长，来提高焊接部分的疲劳寿命和可靠性关于包括模块型半导体器件的部件之间的焊料接合部分。解决方案：在模块型半导体器件中，功率半导体芯片3安装在封装在铜基板1上的绝缘基板2的导体图案2a上，引线框4连接到铜基板1的上表面电极半导体芯片。在这样的模块型半导体器件中焊接各个部件并粘合它们的表面时，通过在包括半导体芯片3的每个接合部件的焊接接合表面上对作为表面处理的Ni进行表面处理来形成Ni膜9.此外，Cu膜10是在Ni膜的表面上形成厚度（≤1μm）的表面，以便在焊接步骤中完全溶解，然后通过富含Sn的焊接将这些部件焊接。因此，在焊料的接合界面上产生Cu-Ni-Sn的三元金属化合物，该金属化合物在实际使用中成为阻碍Ni的洗脱和金属化合物在带电和加热的生长的屏障，由此提高焊料接合部的可靠性。版权所有（C）2006，JPO＆NCIPI

3. 发明专利

JP2005259880A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2005259880A
公开(公告)日：2005-09-22
申请号：JP2004067491
申请日：2004-03-10
申请人： Fuji Electric Holdings Co Ltd , 富士電機ホールディングス株式会社
发明人： YOSHIHARA KATSUHIKO , IKEDA YOSHINARI , IIZUKA YUJI , FUJII TAKASHI , YAMASHITA MITSUO
IPC分类号： H01L21/60 , H01L21/607 , H01L23/50
CPC分类号： H01L2224/37 , H01L2224/37147 , H01L2224/40 , H01L2224/40225 , H01L2224/84 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/1305 , H01L2924/13055 , H01L2924/15787 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To secure high bonding strength by positively destroying an oxide film in the process of ultrasonic bonding of a lead frame without requiring pretreatment of removing the oxide film generated on the metal surface of the conductor pattern of an insulating substrate of a semiconductor element mounting the conductor pattern. SOLUTION: The lead frame 4 ultrasonic-bonded to a circuit board is obtained by forming the conductor pattern 2b on the insulating substrate 2a or the semiconductor mounted on the circuit board. Protrusions 4b whose height is at least equal to or larger than the film thickness of the oxide film 6 generated on the surface of the conductor pattern 2a on the opposite side of bonding are formed on the bonding surface of the bonding leg part 4a of the lead frame. In the state of pressing the protrusions to bonding of a member on the opposite side, ultrasonic vibration is applied by a bonding tool 8 for bonding. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了在引线框架的超声波接合的过程中通过积极地破坏氧化膜来确保高的结合强度，而不需要去除在绝缘基板的导体图案的金属表面上产生的氧化膜的预处理安装导体图案的半导体元件。解决方案：通过在绝缘基板2a或安装在电路板上的半导体上形成导体图案2b来获得超声波接合到电路板的引线框架4。引线4b的高度至少等于或大于在接合的相对侧上的导体图案2a的表面上产生的氧化膜6的膜厚度，在引线的接合腿部4a的接合表面上形成帧。在将突起按压到相对侧的构件的接合状态下，通过用于接合的接合工具8施加超声波振动。版权所有（C）2005，JPO＆NCIPI

4. 发明专利

JP2006049456A Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：JP2006049456A
公开(公告)日：2006-02-16
申请号：JP2004226310
申请日：2004-08-03
申请人： Fuji Electric Holdings Co Ltd , 富士電機ホールディングス株式会社
发明人： YOSHIHARA KATSUHIKO , IKEDA YOSHINARI , YAMASHITA MITSUO
IPC分类号： H01L21/607 , H01L25/07 , H01L25/18
CPC分类号： H01L2224/37 , H01L2224/37147 , H01L2224/40 , H01L2224/40095 , H01L2224/40225 , H01L2924/13055 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide an ultrasonic jointing method improved so that high junction intensity may be secured under the conditions of lower load and low ultrasonic vibration energy when carrying out ultrasonic junction of a lead frame to a circuit board. SOLUTION: The end face of a lead frame 4 for wiring is superposed on the top of a conductor pattern 2b of an insulating substrate 2a, and an ultrasonic jointing method of a lead frame for directly metal junction is carried out by adding pressure force and supersonic vibration to a bonded surface, via an ultrasonic bonding tool 8 pressed on the lead frame. Further, while heating the junction work with a heater 9 so as to make such a preheated high temperature state where it is easy to soften and to provide plastic flow, inert gas is sprayed on the bonded surface from a gas injection nozzle 10 so that this bonded surface may be isolated from a surrounding air atmosphere for preventing the rapid growth of an oxide film. In this state, the bonding tool is pressed so as to carry out the ultrasonic junction. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种改进的超声波接合方法，使得当在引线框架到电路板的超声波接合时，在低负载和低超声波振动能量的条件下可以确保高结强度。解决方案：用于布线的引线框架4的端面叠置在绝缘基板2a的导体图案2b的顶部上，并且通过添加压力来执行用于直接金属结的引线框架的超声波接合方法通过按压在引线框架上的超声焊接工具8，对接合表面施加力和超音速振动。另外，在利用加热器9进行加热加热的同时，使其易于软化并提供塑性流动的预热高温状态，从气体注入喷嘴10向接合面喷射惰性气体，粘合表面可以与周围空气气氛隔离，以防止氧化膜的快速生长。在该状态下，按压接合工具以进行超声波接合。版权所有（C）2006，JPO＆NCIPI

5. 发明专利

JP2008091801A Semiconductor device, and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2008091801A
公开(公告)日：2008-04-17
申请号：JP2006273527
申请日：2006-10-05
申请人： Fuji Electric Holdings Co Ltd , 富士電機ホールディングス株式会社
发明人： YAMASHITA MITSUO
IPC分类号： H01L23/48 , B23K1/00 , B23K35/22 , B23K35/26 , B23K101/40 , C22C13/00
CPC分类号： H01L2224/34 , H01L2224/48091 , H01L2224/49111 , H01L2224/73265 , H01L2224/77272 , H01L2224/83801 , H01L2224/84801 , H01L2924/00014 , H01L2924/01322 , H01L2924/351 , H01L2924/00 , H01L2224/37099 , H01L2224/37599 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To achieve a jointing part excellent in thermal resistance and thermal fatigue, and face-jointing a wiring conductor to a surface electrode of a semiconductor device and jointing the semiconductor device to a conductor substrate with high positional precision, using a soldering material free from lead. SOLUTION: A solder paste of a Sn3.5Ag0.5Cu particle (melting temperature: 220°C) is applied on the surface of a conductor substrate 12; and a semiconductor device 14 is placed thereon. A cream solder of mixed particles (solidus temperature: 220°C, liquidus temperature: 345°C) of a Sn20Ag20Cu0.4Ni powder and a Sn3.5Ag0.5Cu0.07Ni0.01Ge powder in the weight ratio of 62:35, is applied on a surface electrode of the semiconductor device 14; and a wiring conductor 16 is placed thereon. The resultant is heated at 250°C in this state to melt the solder paste of the Sn3.5Ag0.5Cu particle and to make the cream solder of a Sn14.2Ag13.2Cu0.28Ni0.035Ge in total composition into a solid-liquid coexistence state. Then, the resultant is cooled to joint the conductor substrate 12, the semiconductor device 14 and the wiring conductor 16 through the Sn3.5Ag0.5Cu jointing material 17 and the Sn14.2Ag13.2Cu0.28Ni0.035Ge jointing material 15. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题为了实现热阻和热疲劳性优异的接合部分，并且将布线导体面对半导体器件的表面电极并且将半导体器件以高位置精度接合到导体基板，使用不含铅的焊接材料。解决方案：将Sn3.5Ag0.5Cu颗粒的焊膏（熔化温度：220℃）施加到导体基板12的表面上; 并且在其上放置半导体器件14。将Sn20Ag20Cu0.4Ni粉末和Sn3.5Ag0.5Cu0.07Ni0.01Ge粉末的重量比为62:35的混合颗粒（固相线温度：220℃，液相线温度：345℃）的膏状糊料施加在半导体器件14的表面电极上; 并且布线导体16放置在其上。在该状态下将所得物在250℃下加热以熔化Sn3.5Ag0.5Cu颗粒的焊膏，并使Sn14.2Ag13.2Cu0.28Ni0.035Ge的膏状焊料的总组成变为固液共存州。然后，将所得物冷却，通过Sn3.5Ag0.5Cu接合材料17和Sn14.2Ag13.2Cu0.28Ni0.035Ge接合材料15将导体基板12，半导体器件14和布线导体16接合。版权所有（C）2008，JPO＆INPIT

6. 发明专利

JP2008085368A Semiconductor chip and semiconductor device using it 有权
标题翻译：半导体芯片和半导体器件使用它
公开(公告)号：JP2008085368A
公开(公告)日：2008-04-10
申请号：JP2007324218
申请日：2007-12-17
申请人： Fuji Electric Holdings Co Ltd , 富士電機ホールディングス株式会社
发明人： IKEDA YOSHINARI , FUJII TAKASHI , YOSHIHARA KATSUHIKO , IIZUKA YUJI , YAMASHITA MITSUO
IPC分类号： H01L23/48
CPC分类号： H01L2224/45124 , H01L2224/48091 , H01L2224/73221 , H01L2224/73265 , H01L2924/1305 , H01L2924/13055 , H01L2924/19107 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To secure the reliability of a solder-jointing part between a semiconductor chip and a connection conductor. SOLUTION: An Ni plating layer 5 is formed on an Al electrode 3 on the surface side of the semiconductor chip 1 using the electroless plating by the zincate method. Since the Ni plating layer 5 is selectively deposited on the Al electrode 3, the Ni plating layer 5 is not formed on a circumferential voltage-withstanding structure 4 part. The Ni plating layer 5 to be formed can be formed uniformly in a predetermined thickness. Then, a Au plating layer 6 is formed on the Ni plating layer 5. By using the electroless plating, the Au plating layer 6 also is selectively and uniformly formed on the Ni plating layer 5 as in the case of the Ni plating layer 5. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：确保半导体芯片和连接导体之间的焊接部分的可靠性。解决方案：使用锌酸盐法进行化学镀，在半导体芯片1的表面侧的Al电极3上形成Ni镀层5。由于在Al电极3上选择性地沉积Ni镀层5，所以不会在周向耐压结构体4部分形成Ni镀层5。要形成的镀镍层5可以均匀地形成为预定厚度。然后，在Ni镀层5上形成Au镀层6.通过使用化学镀，也可以如Ni镀层5那样在Ni镀层5上选择性地均匀地形成Au镀层6。版权所有（C）2008，JPO＆INPIT

7. 发明专利

JP2006269682A Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2006269682A
公开(公告)日：2006-10-05
申请号：JP2005084778
申请日：2005-03-23
申请人： Fuji Electric Holdings Co Ltd , 富士電機ホールディングス株式会社
发明人： YAMASHITA MITSUO , IKEDA YOSHINARI
IPC分类号： H01L21/60
CPC分类号： H01L24/29 , H01L24/73 , H01L2224/32225 , H01L2224/40 , H01L2224/40095 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/77272 , H01L2224/83801 , H01L2224/8384 , H01L2224/84801 , H01L2924/00014 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/00012 , H01L2224/37099
摘要： PROBLEM TO BE SOLVED: To surface-joint a wiring conductor to the electrode surface of a semiconductor element using a jointing material with no lead, and to joint the semiconductor element to a conductor substrate at high positional precision. SOLUTION: The surface electrode of a semiconductor electrode 14 is jointed to a wiring conductor 16 through a sintered compact 17 of fine metal particles, while the surface electrode of the semiconductor element 14 is jointed to a conductor substrate 12 through a lead-free solder material 15. In manufacturing of the semiconductor substrate like this, the surface electrode of the semiconductor element 14 is pasted first to the wiring conductor 16 through the paste containing fine metal particles, which is heated to sinter the fine metal particles for jointing. Then, the rear surface electrode of the semiconductor element 14 is pasted to the conductor substrate 12 through a lead-free solder paste, and heated for solder jointing. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：使用没有引线的接合材料将布线导体表面接合到半导体元件的电极表面，并且以高位置精度将半导体元件接合到导体基板。解决方案：半导体电极14的表面电极通过金属微粒的烧结体17接合到布线导体16，半导体元件14的表面电极通过引线接合部分接合到导体基板12，在制造这样的半导体衬底时，半导体元件14的表面电极首先通过含有金属微粒的糊料粘贴到布线导体16，该金属颗粒被加热以烧结金属微粒用于接合。然后，将半导体元件14的背面电极通过无铅锡膏粘贴到导体基板12上，进行焊接加热。版权所有（C）2007，JPO＆INPIT

8. 发明专利

JP2005236019A Manufacturing method of semiconductor device 审中-公开
标题翻译：半导体器件的制造方法
公开(公告)号：JP2005236019A
公开(公告)日：2005-09-02
申请号：JP2004043097
申请日：2004-02-19
申请人： Fuji Electric Holdings Co Ltd , 富士電機ホールディングス株式会社
发明人： IKEDA YOSHINARI , NISHIZAWA TATSUO , MOCHIZUKI EIJI , YAMASHITA MITSUO , IIZUKA YUJI
IPC分类号： B23K1/00 , B23K101/40 , H01L21/60
CPC分类号： H01L2224/36 , H01L2224/40 , H01L2224/40095 , H01L2224/40225 , H01L2224/73221 , H01L2224/73265 , H01L2224/77272 , H01L2224/83801 , H01L2224/84801 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/1305 , H01L2924/13055 , H01L2924/00 , H01L2224/37099 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To form a desired and uniform thickness without inclination in a solder junction layer of a semiconductor chip and the other constituent member or a solder junction layer of other constituent members, and to suppress over a long term the growth of an undesirable alloy layer in each of the solder junction layers. SOLUTION: An Ni film is formed on the solder junction surface of each of a semiconductor chip 1, a lead frame 21, an insulating substrate 3, and a heatsink 6. Cream solder is printed on the heatsink 6 on which a filler 31 containing Cu is put. On the filler, the insulating substrate 3 is put on which the cream solder is printed, on which the filler 31 is put. Likewise, the semiconductor chip 1 and the lead frame 21 are put. When the cream solder is melted, and the filler 31 falls to the solder layer and is hardened, the solder junction layers 5, 2, 22 and 23 each having a desired and uniform thickness are yielded. On a junction interface, a Cu-Ni-Sn alloy is formed to suppress the growth of a hard and fragile alloy layer. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了在半导体芯片的焊接接合层和其他构成部件或其它构成部件的焊接层中形成没有倾斜的期望且均匀的厚度，并且长期抑制生长在每个焊接接合层中不合适的合金层。解决方案：在半导体芯片1，引线框架21，绝缘基板3和散热器6的焊接接合面上形成Ni膜。将膏状焊料印刷在散热器6上，在其上填充有填料放入含有铜的31块。在填料上，放置填充有填充物31的膏状焊膏的绝缘基板3。同样地，放置半导体芯片1和引线框架21。当膏状焊料熔化并且填料31落入焊料层并硬化时，产生均匀厚度的焊料接合层5,2,22和23。在接合界面上，形成Cu-Ni-Sn合金以抑制硬和脆性合金层的生长。版权所有（C）2005，JPO＆NCIPI

9. 发明专利

JP2005129886A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005129886A
公开(公告)日：2005-05-19
申请号：JP2004022222
申请日：2004-01-29
申请人： Fuji Electric Holdings Co Ltd , 富士電機ホールディングス株式会社
发明人： IKEDA YOSHINARI , YOSHIHARA KATSUHIKO , IIZUKA YUJI , MOCHIZUKI EIJI , FUJII TAKASHI , YAMASHITA MITSUO
IPC分类号： H01L23/34 , H01L21/60
CPC分类号： H01L24/91 , H01L2224/292 , H01L2224/29298 , H01L2224/37124 , H01L2224/37147 , H01L2224/3754 , H01L2224/40 , H01L2224/40095 , H01L2224/40225 , H01L2224/45 , H01L2224/45124 , H01L2224/48091 , H01L2224/73219 , H01L2224/73221 , H01L2224/73263 , H01L2224/73265 , H01L2224/77272 , H01L2224/83138 , H01L2224/83801 , H01L2224/84 , H01L2224/84801 , H01L2924/01006 , H01L2924/01013 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1305 , H01L2924/13055 , H01L2924/19107 , H01L2924/30105 , H01L2924/351 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To enhance the reliability of the soldered junctions between a semiconductor chip and other component members and the reliability of the soldered junctions between component members except the semiconductor chip. SOLUTION: A thickness of a solder bonding layer 23 for bonding an electrode provided on the surface of a semiconductor chip 1 and lead frame 21 is made into a thickness of ≥ 100 μm. The thermal stress and the distortion generated in the solder bonding layer 23 due to the difference in the coefficients of linear expansion between the semiconductor chip 1 and the lead frame 21 are reduced. In addition, a thickness of the solder bonding layer for bonding a soldered junction between a heatsink and an insulating substrate and a soldered junction between the insulating substrate and the semiconductor chip 1 is made into a thickness of ≥ 100 μm, and the thermal stress and the distortion are reduced. When the heatsink is not bonded, a thickness of the solder bonding layer 23 for bonding the electrode provided on the surface of the semiconductor chip 1 and the lead frame 21 is made into a thickness of ≥ 50 μm. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提高半导体芯片和其它部件之间的焊接接头的可靠性以及除了半导体芯片之外的部件之间的焊接接头的可靠性。解决方案：将设置在半导体芯片1和引线框架21的表面上的电极接合的焊料接合层23的厚度制成≥100μm的厚度。由于半导体芯片1和引线框架21之间的线膨胀系数的差异导致的焊接接合层23产生的热应力和失真减小。另外，将绝缘基板与半导体芯片1之间的散热器和绝缘基板之间的焊接接合部的焊接接合层的厚度设定为≥100μm的厚度，将热应力失真减少。当不结合散热器时，将设置在半导体芯片1的表面上的电极和引线框21接合的焊料接合层23的厚度制成≥50μm的厚度。版权所有（C）2005，JPO＆NCIPI

10. 发明专利

JP2004141878A Lead-free solder material 有权
标题翻译：无铅焊料
公开(公告)号：JP2004141878A
公开(公告)日：2004-05-20
申请号：JP2002306045
申请日：2002-10-21
申请人： Asami Makoto , Fuji Electric Holdings Co Ltd , 富士電機ホールディングス株式会社 , 浅見真
发明人： AMANO AKIRA , FURUHATA HIROAKI , KUBOYAMA TAKAHIRO , MAKITA KAZUYUKI , YAMASHITA MITSUO , MURATA TORU , ASAGI TAKESHI
IPC分类号： B23K35/22 , B23K35/26 , B23K35/363 , C22C13/00 , C22C13/02 , H05K3/34
摘要： PROBLEM TO BE SOLVED: To provide a lead-free solder material which can easily be made into a foil shape, is good in solderability at a temperature slightly exceeding 300°C, and can join wafers to each other at the heat resistance and joining strength equivalent to or higher than those of the conventional solder materials containing lead. SOLUTION: The lead-free solder material is prepared by fixing fine powder of a solder material of an Sn-Sb system or Sn-Ag system not containing lead, a solvent, such as isopropyl alcohol, of a weak polarity, and a hydrocarbon compound, such as succinic acid, which is soluble in the solvent and has a carboxyl group (-COOH) at one end to a slurry form. COPYRIGHT: (C)2004,JPO

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