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1. 发明专利

JP2005116702A Power semiconductor module 审中-公开
标题翻译：功率半导体模块
公开(公告)号：JP2005116702A
公开(公告)日：2005-04-28
申请号：JP2003347356
申请日：2003-10-06
申请人： Fuji Electric Holdings Co Ltd , 富士電機ホールディングス株式会社
发明人： IKEDA YOSHINARI , FUJII TAKASHI , YOSHIHARA KATSUHIKO , IIZUKA YUJI , YAMASHITA MITSUO
IPC分类号： H01L25/07 , H01L25/18
CPC分类号： H01L2224/37 , H01L2224/37147 , H01L2224/40 , H01L2224/40095 , H01L2224/40225 , H01L2224/45124 , H01L2224/48091 , H01L2224/49111 , H01L2224/73221 , H01L2224/73265 , H01L2224/83801 , H01L2224/84801 , H01L2924/1305 , H01L2924/13055 , H01L2924/19107 , H01L2924/351 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a power semiconductor module that can reduce the surface temperature of a semiconductor device and uniformize its in-plane temperature distribution. SOLUTION: The power semiconductor module temporarily suspends heat generated in a semiconductor device 13 by means of a high thermal conductivity body 20 so as to suppress the surface temperature rise of the semiconductor device 13. Especially, the thermal conductivity of the body 20 is higher than that of the semiconductor device 13, so that the generated heat is conducted swiftly, resulting in permitting temperature suppression effect exhibited. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供能够降低半导体器件的表面温度并使其面内温度分布均匀化的功率半导体模块。解决方案：功率半导体模块通过高导热体20临时悬挂在半导体器件13中产生的热量，以便抑制半导体器件13的表面温度升高。特别地，主体20的热导率高于半导体装置13，从而迅速地进行产生的热量，从而可以实现温度的抑制效果。版权所有（C）2005，JPO＆NCIPI

2. 发明专利

JP2005051084A Semiconductor chip and semiconductor device using this 有权
标题翻译：半导体芯片和半导体器件使用此
公开(公告)号：JP2005051084A
公开(公告)日：2005-02-24
申请号：JP2003282270
申请日：2003-07-30
申请人： Fuji Electric Holdings Co Ltd , 富士電機ホールディングス株式会社
发明人： IKEDA YOSHINARI , FUJII TAKASHI , YOSHIHARA KATSUHIKO , IIZUKA YUJI , YAMASHITA MITSUO
IPC分类号： H01L21/28 , H01L21/288 , H01L21/3205 , H01L21/52 , H01L23/52
CPC分类号： H01L2224/45124 , H01L2224/48091 , H01L2224/73265 , H01L2924/1305 , H01L2924/13055 , H01L2924/19107 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To secure the reliability of the solder connections between the conductors. SOLUTION: By using electroless plating, an Ni plating layer 5 is formed on an Al electrode 3 on the front surface of a semiconductor chip 1. On the Al electrode 3, the Ni plating layer 5 is selectively deposited. Thus, the Ni plating layer 5 is not formed at the part of a peripheral voltage resistant structure 4. The formed Ni plating layer 5 can be evenly formed in a prescribed thickness. Continually, an Au-plating layer 6 is formed on the Ni plating layer 5. By using electroless plating, the Au-plating layer 6 is selectively and evenly formed on the Ni plating layer 5 similarly to the Ni plating layer 5. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：确保导体之间焊料连接的可靠性。解决方案：通过使用化学镀，在半导体芯片1的前表面上的Al电极3上形成Ni镀层5.在Al电极3上，选择性地沉积Ni镀层5。因此，在周边耐电压结构4的部分没有形成Ni镀层5.可以将所形成的Ni镀层5均匀地形成为规定厚度。继续在Ni镀层5上形成镀层6.通过使用化学镀，与Ni镀层5同样地，在镀镍层5上选择性均匀地形成Au镀层6。版权所有（C）2005，JPO＆NCIPI

3. 发明专利

JP2005039135A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2005039135A
公开(公告)日：2005-02-10
申请号：JP2003276436
申请日：2003-07-18
申请人： Fuji Electric Holdings Co Ltd , 富士電機ホールディングス株式会社
发明人： YOSHIHARA KATSUHIKO
IPC分类号： H01L23/36 , H01L23/373
CPC分类号： H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To increase a heat radiating effect without lowering a reliability. SOLUTION: A semiconductor chip 3 is joined to a collector side copper circuit pattern 1 through a solder joined part 2. Further, the upper surface of the semiconductor chip 3 is connected to a forked lead frame 7 joined by branching to a first emitter side copper circuit pattern 5a and a second emitter side copper circuit pattern 5b through a solder joined part 4. Heat generated from the semiconductor chip 3 is radiated from the collector side copper circuit pattern 1 on the back of the chip, and also the heat transmits on each path of the forked lead frame 7 to the first emitter side copper circuit pattern 5a and the second emitter side copper circuit pattern 5b for radiation of heat. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提高散热效果而不降低可靠性。解决方案：半导体芯片3通过焊料接合部分2接合到集电体侧铜电路图案1.此外，半导体芯片3的上表面连接到通过分支连接到第一发射极侧铜电路图案5a和第二发射极侧铜电路图案5b。通过焊料接合部4从半导体芯片3产生的热量从芯片背面的集电体侧铜电路图案1照射，在分叉引线框架7的每个路径上向第一发射极侧铜电路图案5a和第二发射极侧铜电路图案5b发送热辐射。版权所有（C）2005，JPO＆NCIPI

4. 发明专利

JP2007048889A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2007048889A
公开(公告)日：2007-02-22
申请号：JP2005230953
申请日：2005-08-09
申请人： Fuji Electric Holdings Co Ltd , 富士電機ホールディングス株式会社
发明人： YOSHIHARA KATSUHIKO
IPC分类号： H01L29/739 , H01L21/336 , H01L23/29 , H01L29/78
CPC分类号： H01L2224/45124 , H01L2224/48 , H01L2224/48091 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device wherein a heat spreader is fastened to a semiconductor chip by solder and cracks are prevented from appearing from the upper corners of the ends of a polyimide film covering gate liners to the inside of the solder. SOLUTION: An oxide film 2 is formed on a semiconductor substrate 1, and a polysilicon interconnection 3 connected to a gate electrode of IGBT of polysilicon is formed on top of the oxide film 2. Then, an insulation film 4 is formed and openings 5 are formed therein. The gate liners 6 and 7 and the polysilicon interconnection 3 are connected via the openings 5. The emitter region of the IGBT and a plurality of emitter electrodes 9 are also connected via the openings 5. The gate liners 6 and 7 are covered by polysilicon films 10 and 11. The upper corners of the ends of the polyimide film 10 on the gate liner 6 put between the emitter electrodes 9 are rounded to reduce stress applied on the corners in a repetitious cooling and heating environment. Consequently, cracks can be prevented from appearing in the solder 13 for fastening the heat spreader 12 to the emitter electrodes 9. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种半导体器件，其中散热器通过焊料紧固到半导体芯片，并且防止从覆盖栅极衬垫的聚酰亚胺膜的端部的上角出现裂纹焊接。解决方案：在半导体衬底1上形成氧化物膜2，并且在氧化膜2的顶部上形成连接到多晶硅的IGBT的栅电极的多晶硅互连3。然后形成绝缘膜4，在其中形成开口5。栅极衬套6和7以及多晶硅互连3经由开口5连接。IGBT的发射极区域和多个发射极电极9也经由开口5连接。栅极衬套6和7被多晶硅膜覆盖位于发射电极9之间的栅极衬垫6上的聚酰亚胺膜10的端部的上角被倒圆，以减少在重复的冷却和加热环境中施加在拐角上的应力。因此，可以防止在用于将散热器12紧固到发射极9的焊料13中出现裂缝。版权所有（C）2007，JPO＆INPIT

5. 发明专利

JP2006135270A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2006135270A
公开(公告)日：2006-05-25
申请号：JP2004338399
申请日：2004-11-24
申请人： Fuji Electric Holdings Co Ltd , 富士電機ホールディングス株式会社
发明人： YOSHIHARA KATSUHIKO , FUJII TAKASHI
IPC分类号： H01L21/60 , H01L21/607
CPC分类号： H01L2224/32225 , H01L2224/37124 , H01L2224/37147 , H01L2224/376 , H01L2224/39 , H01L2224/4007 , H01L2224/45 , H01L2224/45015 , H01L2224/45124 , H01L2224/48091 , H01L2224/48227 , H01L2224/48472 , H01L2224/49111 , H01L2224/73265 , H01L2224/77 , H01L2224/84 , H01L2224/84205 , H01L2224/84801 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/1305 , H01L2924/13055 , H01L2924/2076 , H01L2924/30105 , H01L2924/00 , H01L2224/37599 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a method that relaxes heat generation concentration on the semiconductor chip, increases heat dissipation on the upper surface of the chip, enables modular assembly construction with an improved power cycle durability, and facilitates wiring lead connection to effectively manufacture a power semiconductor device with a semiconductor chip solder-mounted on an insulated substrate. SOLUTION: This method forms a wiring structure by laminating a strap metal foil 11 on the top surface of a heat spreader as a wiring lead, and joining them with supersonic waves. When joining the heat spreader and the metal foil with supersonic waves in a manufacturing process, this method forms a projection on a supersonic horn edge by knurling so that damages to the solder chip and solder junction can be prevented and a power distribution channel with a required joint area can be reserved for supersonic joint between the heat spreader and the metal foil, and then presses the above projection against the surface of the metal foil during supersonic joint, so that press load and supersonic vibration can be applied to a target joint location and a supersonic interface corresponding to a required current-carrying capacity can be disposed dispersedly in the overlapping area between the heat spreader and the metal foil. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了提供一种放松半导体芯片上的发热浓度的方法，增加了芯片上表面的散热，使模块化的组装结构具有改善的动力循环耐久性，并且有助于将引线连接到有效地制造具有焊接安装在绝缘基板上的半导体芯片的功率半导体器件。解决方案：该方法通过将带状金属箔11层叠在散热器的顶表面上作为布线引线并与超声波接合来形成布线结构。当在制造过程中连接散热器和具有超声波的金属箔时，该方法通过滚花在超音速喇叭边缘上形成投射，从而可以防止对焊料芯片和焊接点的损坏，并且具有所需的配电通道关节面积可以预留在散热器和金属箔之间的超音速接头，然后在超声波接头处将上述突起压在金属箔的表面上，使得压力负载和超音速振动可以应用于目标接头位置，对应于所需的载流能力的超音速界面可以分散地布置在散热器和金属箔之间的重叠区域中。版权所有（C）2006，JPO＆NCIPI

6. 发明专利

JP2005223229A Bonding method, manufacturing method of semiconductor apparatus using the same, and semiconductor apparatus 审中-公开
标题翻译：接合方法，使用其的半导体装置的制造方法和半导体装置
公开(公告)号：JP2005223229A
公开(公告)日：2005-08-18
申请号：JP2004031519
申请日：2004-02-09
申请人： Fuji Electric Holdings Co Ltd , 富士電機ホールディングス株式会社
发明人： YOSHIHARA KATSUHIKO , IKEDA YOSHINARI , YAMASHITA MITSUO
IPC分类号： H01L21/607 , H01L21/60
CPC分类号： H01L2224/40 , H01L2224/45124 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/30105 , H01L2924/00 , H01L2224/48 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To exclude the oxide films formed on the surfaces of metal materials when bonding the metal materials to each other, without using such a large-sized equipment as a reduction furnace in the ultrasonic bonding of metals. SOLUTION: Micro-grains 4 are so interposed between the bonding surfaces of two metal members (1, 2), and ultrasonic vibrations are so applied to at least one of the metal members as to bond the metal members to each other. As the micro-grains, there are used the ones whose grain sizes are not smaller than the larger thickness of the thicknesses of the natural oxide films formed on the bonding surfaces of the two metal members. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：待解决的问题：为了排除在金属材料彼此接合时形成在金属材料表面上的氧化膜，而不使用金属超声波接合中的这种大型设备作为还原炉。解决方案：微晶粒4被插入在两个金属构件（1,2）的接合表面之间，并且超声波振动被施加到至少一个金属构件以将金属构件彼此接合。作为微粒，使用粒径不小于形成在两个金属构件的接合表面上的自然氧化膜的厚度的较大厚度的微粒。版权所有（C）2005，JPO＆NCIPI

7. 发明专利

JP2005064441A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2005064441A
公开(公告)日：2005-03-10
申请号：JP2003326367
申请日：2003-09-18
申请人： Fuji Electric Holdings Co Ltd , 富士電機ホールディングス株式会社
发明人： IIZUKA YUJI , IKEDA YOSHINARI , YOSHIHARA KATSUHIKO , YAMASHITA MITSUO
IPC分类号： H01L23/34 , H01L21/60
CPC分类号： H01L2224/48091 , H01L2224/48227 , H01L2924/1305 , H01L2924/13055 , H01L2924/19107 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To secure high reliability without spoiling heat emissivity. SOLUTION: In a semiconductor device, a lead frame 6 functioning as a current path and a heat radiation path for radiating the heat of a semiconductor chip 1 has a stress dispersion shape part for cutting off or dispersing stress applied to the join layer or corner part near a chip join plane 7 as a join plane for a join layer 8 fixed to the surface of the semiconductor chip 1 or a wiring board 2, or nearby a corner part where stress is converged. This stress dispersion shape part cuts off or disperses at least part of the stress to reduce stress effect of thermal stress, generated by the heat generation of the semiconductor chip 1, on the brittle or soft join layer. The stress dispersion shape part includes, for example, a slit shape, a chamfered shape, a bored shape, etc., to cut off or reduce transmission of stress. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：确保高可靠性而不破坏热辐射率。解决方案：在半导体器件中，用作电流路径的引线框架6和用于辐射半导体芯片1的热的散热路径具有用于切断或分散施加到接合层的应力的应力分散形状部分或作为用于固定在半导体芯片1或布线基板2的表面上的接合层8的接合面的芯片接合面7附近的角部或者应力集中的角部附近。该应力分散形状部分切断或分散至少部分应力，以减少由于半导体芯片1的发热产生的热应力对脆性或软接合层的应力影响。应力分散形状部包括例如狭缝形状，倒角形状，钻孔形状等，以切断或减少应力的传递。版权所有（C）2005，JPO＆NCIPI

8. 发明专利

JP2008028286A Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：JP2008028286A
公开(公告)日：2008-02-07
申请号：JP2006201588
申请日：2006-07-25
申请人： Fuji Electric Holdings Co Ltd , 富士電機ホールディングス株式会社
发明人： YOSHIHARA KATSUHIKO , SATO KEISUKE , GOTOU TOMOAKI
IPC分类号： H01L23/50 , H01L21/60 , H01L23/48
CPC分类号： H01L2224/37011 , H01L2224/37147 , H01L2224/40 , H01L2224/40137 , H01L2224/40139 , H01L2224/40225 , H01L2224/84 , H01L2224/84801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/01088 , H01L2924/014 , H01L2924/1305 , H01L2924/13055 , H01L2924/15787 , H01L2924/30105 , H01L2924/00 , H01L2924/00014 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide an improved method for laser-welding of a lead frame by which high reproducibility welding without variation is achieved utilizing low power laser light. SOLUTION: In the method for manufacturing a semiconductor device; a wiring structure is formed by applying laser light to an upper surface of a junction of a lead frame, and superimposing the junction on a material to be joined, while a heat spreader 5 is mounted on a main upper electrode of a semiconductor chip on an insulating substrate, and a strap-like lead frame 6 as a lead material for the internal wiring is disposed among a conductive pattern of the insulating substrate, a heat spreader, and an input-output terminal. The junction is superimposed on the material to be joined, and the laser light 13 is applied to the upper surface of the lead frame junction to carry out weld joining between the lead frame and the material to be joined (heat spreader) after making coarse the upper surface (or a back surface of the junction of the lead frame or both of the upper and back surfaces). COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于激光焊接引线框架的改进方法，通过该方法利用低功率激光实现高变化的高再现性焊接。解决方案：在制造半导体器件的方法中; 通过将激光施加到引线框架的接合部的上表面并将接合部重叠在待接合材料上而形成布线结构，同时将散热器5安装在半导体芯片的主上电极上绝缘基板和作为内部布线的引线材料的带状引线框架6设置在绝缘基板，散热器和输入 - 输出端子的导电图案中。该接合部叠加在待接合的材料上，激光13被施加到引线框架接合部的上表面，在引导框架和待接合材料（散热器）之间进行粗糙化后的焊接上表面（或引线框架的连接处的后表面或上表面和后表面两者）。版权所有（C）2008，JPO＆INPIT

9. 发明专利

JP2007027308A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2007027308A
公开(公告)日：2007-02-01
申请号：JP2005205471
申请日：2005-07-14
申请人： Fuji Electric Holdings Co Ltd , 富士電機ホールディングス株式会社
发明人： FUJII TAKASHI , IKEDA YOSHINARI , YOSHIHARA KATSUHIKO
IPC分类号： H01L21/52 , H01L29/78 , H01L29/861
CPC分类号： H01L24/32 , H01L2224/45124 , H01L2224/45144 , H01L2924/00014 , H01L2924/1305 , H01L2924/13055 , H01L2924/30107 , H01L2924/00 , H01L2224/48
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which can radiate heat even from the periphery of a semiconductor chip. SOLUTION: An anode area 4 is formed in the surface layer of a semiconductor substrate 3, an insulating film 6 is formed around the outer periphery of the semiconductor substrate 3, and then an anode electrode 7 having a hood 7a is formed on the anode area 4 and the insulating film 6. The anode electrode 7 including the hood 7a is joined with a metal 1 with a first solder layer 9 in-between. The area S3 of the metal 1 is made larger than that S1 of the anode area 4, and smaller than the anode electrode 7. Thus, heat can be radiated even from the outer periphery of the semiconductor chip, and an appropriate solder filet can be also made, resulting in enhancing joint strength by solder. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供即使从半导体芯片的周围也能够散热的半导体器件。解决方案：在半导体基板3的表面层中形成阳极区域4，在半导体基板3的外周形成绝缘膜6，然后在具有罩7a的阳极电极7上形成阳极区域4和绝缘膜6.包括罩7a的阳极电极7与金属1接合，其间具有第一焊料层9。金属1的面积S3大于阳极区域4的S1，并且比阳极电极7小。因此，即使从半导体芯片的外周也可以散热，并且适当的焊料可以也制成，从而通过焊料提高接合强度。版权所有（C）2007，JPO＆INPIT

10. 发明专利

JP2006049456A Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：JP2006049456A
公开(公告)日：2006-02-16
申请号：JP2004226310
申请日：2004-08-03
申请人： Fuji Electric Holdings Co Ltd , 富士電機ホールディングス株式会社
发明人： YOSHIHARA KATSUHIKO , IKEDA YOSHINARI , YAMASHITA MITSUO
IPC分类号： H01L21/607 , H01L25/07 , H01L25/18
CPC分类号： H01L2224/37 , H01L2224/37147 , H01L2224/40 , H01L2224/40095 , H01L2224/40225 , H01L2924/13055 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide an ultrasonic jointing method improved so that high junction intensity may be secured under the conditions of lower load and low ultrasonic vibration energy when carrying out ultrasonic junction of a lead frame to a circuit board. SOLUTION: The end face of a lead frame 4 for wiring is superposed on the top of a conductor pattern 2b of an insulating substrate 2a, and an ultrasonic jointing method of a lead frame for directly metal junction is carried out by adding pressure force and supersonic vibration to a bonded surface, via an ultrasonic bonding tool 8 pressed on the lead frame. Further, while heating the junction work with a heater 9 so as to make such a preheated high temperature state where it is easy to soften and to provide plastic flow, inert gas is sprayed on the bonded surface from a gas injection nozzle 10 so that this bonded surface may be isolated from a surrounding air atmosphere for preventing the rapid growth of an oxide film. In this state, the bonding tool is pressed so as to carry out the ultrasonic junction. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种改进的超声波接合方法，使得当在引线框架到电路板的超声波接合时，在低负载和低超声波振动能量的条件下可以确保高结强度。解决方案：用于布线的引线框架4的端面叠置在绝缘基板2a的导体图案2b的顶部上，并且通过添加压力来执行用于直接金属结的引线框架的超声波接合方法通过按压在引线框架上的超声焊接工具8，对接合表面施加力和超音速振动。另外，在利用加热器9进行加热加热的同时，使其易于软化并提供塑性流动的预热高温状态，从气体注入喷嘴10向接合面喷射惰性气体，粘合表面可以与周围空气气氛隔离，以防止氧化膜的快速生长。在该状态下，按压接合工具以进行超声波接合。版权所有（C）2006，JPO＆NCIPI

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